Process for manufacturing a dual charge storage location memory cell

#The present invention relates generally to the field of semiconductor memories, particularly non-volatile memories and still more particularly to electrically programmable non-volatile memories. More specifically, the invention concerns dual charge storage location non-volatile semiconductor memory cells and, in particular, the manufacturing thereof.

#As known, the information storage mechanism in non-volatile memory cells such as EPROMs, EEPROMs and Flash EEPROMs is based on the possibility of having an electric charge trapped in a charge storage element. The presence of the electric charge in the charge storage element causes a change in the memory cell threshold voltage, that can be assessed by measuring a current sunk by the memory cell in a prescribed bias condition.

#Typically, the charge storage element is represented by a polysilicon floating gate insulatively placed over the memory cell channel region and capacitively coupled to a control gate. Charge carriers can be injected into the floating gate by means of the hot electron injection mechanism, as in EPROMs and Flash EPROMs, or by tunnelling, as in EEPROMs. The presence of an electric charge in the floating gate affects the formation of a conductive channel in the channel region.

#The features and advantages of the present invention will be made apparent by the following detailed description of some embodiments thereof, provided merely by way of non-limitative examples with reference to the attached drawings, wherein:

#FIGS. 1A to 1K are cross-sectional views showing some steps of a manufacturing process according to a first embodiment of the present invention;

#FIG. 1L is an enlarged cross-sectional view of a dual charge storage location memory cell obtained by the process according to the first embodiment of the invention;

#In the following, same reference numerals will be adopted to identify same parts in the different embodiments of the invention, which will be described.

#FIGS. 1A to 1K are schematic cross-sectional views showing a portion of a memory cell array during the main steps of a manufacturing process according to a first embodiment of the present invention.

#With reference to FIG. 1A, reference numeral 11 indicates a semiconductor, e.g. silicon, substrate, or alternatively a doped well formed in a semiconductor substrate (in this case, the substrate being not visible in the drawings). In the context of this description the term substrate is to be intended as encompassing both of the alternatives. For example, the semiconductor substrate is of the P conductivity type and has a doping level of 1015 to 1018 atoms/cm3.