Methods of fabricating flash memory cell having split-gate structure using spacer oxidation process

A method of fabricating a flash memory cell, comprising the steps of:

• defining an active area by forming an isolation layer on a semiconductor substrate;
• forming a first gate insulating layer, a floating gate layer and an oxidation barrier layer on the active area, sequentially;
• forming an oxidation barrier pattern having an opening to expose a portion of the floating gate layer by patterning the oxidation barrier layer, wherein both ends of the opening overlap with the isolation layer;
• forming a spacer on a side of the opening;
• forming an inter-gate oxide layer pattern in the opening by oxidizing the spacer and the exposed floating gate layer;
• removing the oxidation barrier pattern;
• forming a floating gate on a lower part of the inter-gate oxide layer pattern by etching the floating gate layer using the inter-gate oxide layer pattern as an etch mask;
• forming a second gate insulating layer on the active area having the floating gate;
• forming a control gate overlapping with a portion of the floating gate on the second gate insulating layer;
• and
• forming a source and a drain separated from each other on the active area between which the floating gate and the control gate are placed.