Gate coupling in floating-gate memory cells
AssigneeMicron Technology, Inc.
InventorPaul J. Rudeck
Life of this patent
Estimating the term…
Abstract
Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.
Claims25
A method of fabricating floating-gate memory cells, comprising:
- forming an isolation region in a semiconductor substrate;
- forming a tunnel dielectric layer overlying the substrate on opposing sides of the isolation region;
- forming a floating-gate layer overlying the tunnel dielectric layer and overlying the isolation region;
- forming a trench in the floating-gate layer overlying the isolation region, wherein the isolation region remains covered by the floating-gate layer after forming the trench;
- forming spacers on sidewalls of the trench, leaving a portion of the floating-gate layer exposed between the spacers;
- removing the exposed portion of the floating-gate layer to expose a portion of the isolation region;
- forming an intergate dielectric layer overlying the floating-gate layer;
- and
- forming a control-gate layer overlying the intergate dielectric layer.
A method of forming a floating-gate memory cell, comprising:
- forming a tunnel dielectric layer overlying an active region of a semiconductor substrate interposed between two isolation regions;
- forming a floating-gate layer overlying the isolation regions and the tunnel dielectric layer;
- removing a first portion of the floating-gate layer overlying a first of the isolation regions, wherein the first isolation region remains covered by the floating-gate layer after removing the first portion of the floating-gate layer;
- removing a second portion of the floating-gate layer overlying a second of the isolation regions, wherein the second isolation region remains covered by the floating-gate layer after removing the second portion of the floating-gate layer;
- removing a third portion of the floating-gate layer overlying the first isolation region to expose a portion of the first isolation region;
- removing a fourth portion of the floating-gate layer overlying the second isolation region to expose a portion of the second isolation region;
- forming an intergate dielectric layer overlying the floating-gate layer and the isolation regions;
- and
- forming a control-gate layer overlying the intergate dielectric layer.
Dependencies are inferred from the claim text.