Semiconductor package having reduced thickness
AssigneeAmkor Technology, Inc.
InventorsTae Heon Lee, Mu Hwan Seo
Life of this patent
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Abstract
A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25–75% of the thickness of the leads.
Claims20
A method of fabricating a semiconductor package, comprising the steps of:
- a) providing a leadframe which includes:
- a die paddle having opposed, generally planar top and bottom surfaces;
- and
- a plurality of leads which extend at least partially about the die paddle and each have opposed, generally planar upper and lower lead surfaces and an inner lead end;
- b) etching the leadframe such that each of the leads includes a half etched portion which is formed in the lower lead surface, extends to the inner lead end, and defines a generally planar etched lead surface which is disposed in opposed relation to the upper lead surface and extends in generally co-planar relation to the top surface of the die paddle;
- c) attaching a semiconductor chip to the top surface of the die paddle;
- d) electrically connecting the semiconductor chip to at least one of the leads;
- and
- e) at least partially encapsulating the leadframe and the semiconductor chip with an encapsulation material such that at least a portion of the lower lead surface of each of the leads is exposed in the encapsulation material.
A method of fabricating a leadframe for use in a semiconductor package, comprising the steps of:
- a) providing a die paddle having opposed, generally planar top and bottom surfaces, and a plurality of leads which extend at least partially about the die paddle and each have opposed, generally planar upper and lower lead surfaces and an inner end;
- and
- b) etching the die paddle and the leads such that each of the leads includes a half etched portion which is formed in the lower lead surface, extends to the inner lead end, and defines a generally planar etched lead surface which is disposed in opposed relation to the upper lead surface and extends in generally co-planar relation to the top surface of the die paddle.
A method of fabricating a semiconductor package, comprising the steps of:
- a) providing a leadframe which includes:
- a die paddle having opposed, generally planar top and bottom surfaces;
- and
- at least one lead which is disposed in spaced relation to the die paddle and has opposed, generally planar upper and lower lead surfaces and an inner end;
- b) etching the leadframe such that the lead includes a half etched portion which is formed in the lower lead surface, extends to the inner lead end, and defines a generally planar etched lead surface which is disposed in opposed relation to the upper lead surface and extends in generally co-planar relation to the top surface of the die paddle;
- and
- c) electrically connecting a semiconductor chip to the lead.
Dependencies are inferred from the claim text.