Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKoichi Kawai
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device including: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of the memory cell array; first data hold circuits configured to hold data for designating whether each column of the memory cell array is defective or not; and a second data hold circuit configured to hold data read out of the first dada hold circuits, and control to skip a defective column address of the memory cell array in accordance with the data read out of the first data hold circuit.
Claims14
A semiconductor memory device comprising:
- a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;
- a sense amplifier circuit configured to read data of said memory cell array;
- first data hold circuits configured to hold data for designating whether each column of said memory cell array is defective or not;
- and
- a second data hold circuit configured to hold data read out of said first data hold circuits, and to control skipping a defective column address of said memory cell array in accordance with the data read out of said first data hold circuits.
An electric card equipped with a semiconductor memory device, said semiconductor memory device comprising:
- a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;
- a sense amplifier circuit configured to read data of said memory cell array;
- first data hold circuits configured to hold data for designating whether each column of said memory cell array is defective or not;
- and
- a second data hold circuit configured to hold data read out of said first data hold circuits, and to control skipping a defective column address of said memory cell array in accordance with the data read out of said first data hold circuits.
A semiconductor memory device comprising:
- a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;
- a sense amplifier circuit configured to read data of said memory cell array;
- data hold circuits so attached to said sense amplifier circuit as to hold data for designating whether each column of said memory cell array is defective or not;
- and
- a shift register, into which data read out of said data hold circuits are serially input, outputs of said shift register serving for skipping a defective column address of said memory cell array.
An electric card equipped with a semiconductor memory device, said semiconductor memory device comprising:
- a memory cell array with electrically rewritable and non-volatile memory cells arranged therein;
- a sense amplifier circuit configured to read data of said memory cell array;
- data hold circuits so attached to said sense amplifier circuit as to hold data for designating whether each column of said memory cell array is defective or not;
- and
- a shift register, into which data read out of said data hold circuits are serially input, outputs of said shift register serving for skipping a defective column address of said memory cell array.
Dependencies are inferred from the claim text.