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US 7,109,906 B1Granted
NICAM encoder featuring synchronization of a NICAM processor with front-end input and output sections
AssigneeFreescale Semiconductor, Inc.
InventorsLuciano Zoso, Allan P. Chin, David P. Lester
Life of this patent
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Abstract
A NICAM encoder (54) comprises a NICAM processor (82) and a front-end section (80,84) coupled to the NICAM processor. The front-end section is configured for operating with a system clock (68) that is integer divisible such that the system clock can be used by both the NICAM processor (82) and the front-end section (80,84).
Claims18
A NICAM encoder comprising:
- a NICAM processor;
- and
- a front-end section coupled to the NICAM processor, wherein the front-end section synchronizes the front-end section and the NICAM processor with timing derived from integer divisions of a single system clock, wherein the front-end section comprises a front-end input section and a front-end output section, the front-end input section coupled to an input of the NICAM processor and the front-end output section coupled to an output of the NICAM processor, wherein the front-end input section comprises one of:
- (a) an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator, or
- (b) a dual-channel analog-to-digital converter (ADC), an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the ADC couples to the interpolator, the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator.
2 more elements
A NICAM encoder comprising:
- a NICAM processor;
- and
- a front-end section coupled to the NICAM processor, wherein the front-end section synchronizes the front-end section and the NICAM processor with timing derived from integer divisions of a single system clock, wherein the front-end section comprises a front-end input section and a front-end output section, the front-end input section coupled to an input of the NICAM processor and the front-end output section coupled to an output of the NICAM processor wherein the front-end output section comprises a digital square-root raised-cosine (SRRC) filter with interpolation factor K, a variable interpolator with variable interpolation factor L, a digital mixer, a digital-to-analog converter (DAC), and a sine & cosine generator, wherein the SRRC filter couples to the variable interpolator, the variable interpolator couples to the mixer, and the mixer couples to the DAC and to the sine & cosine generator.
A NICAM encoder comprising:
- a front-end input section, wherein the front-end input section comprises one of:
- (a) an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator, or
- (b) a dual-channel analog-to-digital converter (ADC), an interpolator by factor N, a first decimator by factor M, a pre-emphasis filter, and a second decimator by factor P, wherein the ADC couples to the interpolator, the interpolator couples to the first decimator, the first decimator couples to the pre-emphasis filter, and the pre-emphasis filter couples to the second decimator;
- a NICAM processor, the front-end input section being coupled to an input of the NICAM processor;
- and
- a front-end output section, wherein the front-end output section comprises a digital square-root raised-cosine (SRRC) filter with interpolation factor K, a variable interpolator with variable interpolation factor L, a digital mixer, a digital-to-analog converter (DAC), and a sine & cosine generator, wherein the SRRC filter couples to the variable interpolator, the variable interpolator couples to the mixer, and the mixer couples to the DAC and to the sine & cosine generator, the NICAM processor being coupled to an input of the front-end output section, wherein the front-end output section provides a synchronization strobe to the NICAM processor with timing derived from integer divisions of a single system clock.
3 more elements
Dependencies are inferred from the claim text.