# US 7,109,749 B2 · Programmable logic devices providing reduced power consumption > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,109,749 B2 - Document ID: US7109749B2 - Status: Granted - Kind: B2 - Application number: 10/449,750 - Filed: 2003-05-29 - Published: 2004-01-15 - Granted: 2006-09-19 - Earliest claimed: 2002-05-29 - Assignees: STMicroelectronics Pvt. Ltd. - Inventors: Namerita Khanna; Parvesh Swami; Deepak Agarwal - Web page: https://patentgrep.com/patent/US7109749B2 ## CPC - H03K 19/1776: for memories - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17784: for supply voltage - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/037: Bistable circuits - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock. ## Claims ### Claim 1 A Programmable Logic Device providing reduction in the power consumption for sequential logic and data storage functions, comprising at least one circuit arrangement including two single-edge-triggered flip-flops that function as a dual-edge-triggered flip-flop operating on both edges of a circuit clock and also function as two independent single-edge-triggered flip-flops operating on a single edge of the circuit clock, with the circuit arrangement being configurable to operate the two single-edge-triggered flip-flops as either a single dual-edge-triggered flip-flop or as two independent single-edge-triggered flip-flops. ### Claim 2 (depends on 1) A Programmable Logic Device as claimed in claim 1, wherein the circuit arrangement comprises two flip-flops, one of which is capable of being configured as rising-edge-triggered while the other is configured as falling-edge-triggered with one of the flip-flops latching data each time the clock changes state while the other remains inactive, the outputs from two flip-flops being selectively enabled as the dual-edge-triggered output by the clock signal. ### Claim 3 (depends on 1) A Programmable Logic Device as claimed in claim 1, wherein the dual-edge-triggered-flip flop comprises two single-edge-triggered flip-flops triggered by two clock sources that are configurable as complimentary clocks for dual-edge-triggered operation or as clocks with the same polarity for single-edge-triggered operation. ### Claim 4 A Programmable Gate Array (PGA) providing reduction in power consumption for sequential logic and data storage functions, comprising at least one circuit arrangement that functions both as a dual-edge-triggered flip-flop operating on both edges of the circuit clock and also functions as two independent single-edge triggered flip-flops operating on a single edge of the circuit clock, with the circuit arrangement being configurable to operate the two single-edge-triggered flip-flops as either a single dual-edge-triggered flip-flop or as two independent single-edge-triggered flip-flops. ### Claim 5 (depends on 4) A Programmable Gate Array as claimed in claim 4, wherein the circuit arrangement comprises two flip-flops, one of which is capable of being configured as rising-edge-triggered while the other is configured as falling-edge-triggered with one of the flip-flops latching data each time the clock changes state while the other remains inactive, the outputs from two flip-flops being selectively enabled as the dual-edge-triggered output by the clock signal. ### Claim 6 A method of enabling reduction in power consumption for sequential logic and data storage functions in a Programmable Logic Device, comprising the step of providing at least one circuit arrangement including two single-edge-triggered flip-flops that are configurable to function as a dual-edge-triggered flip-flop operating on both edges of a circuit clock and to function as two independent single-edge-triggered flip-flops operating on a single edge of the circuit clock with the method further including configuring the circuit arrangement to operate the two single-edge-triggered flip-flops as either a single dual-edge-triggered flip-flop or as two independent single-edge-triggered flip-flops. ### Claim 7 A logic circuit, comprising: a first input node operable to receive a first stream of data values; a second input node operable to receive a second stream of data values; and a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output. ### Claim 8 (depends on 7) The logic circuit of claim 7 wherein the logic circuit comprises first and second single-edge-triggered flip flops. ### Claim 9 (depends on 7) The logic circuit of claim 7 wherein the programmable logic circuit is adapted to receive a plurality of configuration bits, the configuration bits collectively defining the mode of operation of the programmable logic circuit. ### Claim 10 A configurable logic circuit, comprising: a first input node operable to receive a first stream of data values; a second input node operable to receive a second stream of data values; a first output node; a second output node; a clock node operable to receive a clock signal having first-type and second-type edges; and a flip-flop circuit coupled to the input nodes, output nodes, and clock node and, in a dual-edge-triggered mode, operable to, latch a first data value on the first input node and provide the latched first data value on the first output node in response to a first-type edge of the clock signal, and latch a second data value on the first input node and provide the latched second data value on the first output node in response to a second-type edge of the clock signal and, in a single-edge-triggered mode, operable to latch a first data value on the first input node and provide the latched value on the first output node responsive to the first-type edge of the clock signal, and latch a second data value on the second input node and provide the latched value on the second output node responsive to the first-type edge of the clock signal. ### Claim 11 (depends on 10) The logic circuit of claim 10 wherein the flip-flop circuit comprises: a first D flip-flop that in the dual-edge-triggered mode is operable to latch the first data value and provide the latched first data value on the output node in response to the first-type edge of the clock signal; and a second D flip-flop that in the dual-edge-triggered mode is operable to latch the second data value and provide the latched second data value on the output node in response to the second-type edge of the clock signal. ### Claim 12 (depends on 10) The logic circuit of claim 10 wherein: the first-type edges of the clock signal comprise rising edges; and the second-type edges of the clock signal comprise falling edges. ### Claim 13 (depends on 10) The logic circuit of claim 10 wherein: the first-type edges of the clock signal comprise falling edges; and the second-type edges of the clock signal comprise rising edges. ### Claim 14 A logic circuit, comprising: first and second circuit input nodes; first and second circuit output nodes; a first flip-flop having an input node coupled to the first circuit input node, a clock node, and an output node; a second flip-flop having an input node, a clock node, and an output node coupled to the second circuit output node; a first multiplexor operable to couple the clock node of the second flip-flop to a clock signal in a first operational mode and to an inverted clock signal in a second operational mode; a second multiplexor operable to couple the input node of the second flip-flop to the first circuit input node in a second operational mode and to the second circuit input node in the first operational mode; and a third multiplexor operable to couple the output node of the first flip-flop to the first circuit output node in the first operational mode and to alternately couple the output nodes of the first and second flip-flops to the first circuit output node in the second operational mode. ### Claim 15 (depends on 14) The logic circuit of claim 14, further comprising a fourth multiplexor operable to couple the clock signal to a control node of the third multiplexor in the second operational mode. ### Claim 16 A programmable logic block, comprising: a logic circuit, comprising, a first input node operable to receive a first stream of data values; a second input node operable to receive a second stream of data values; and a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output. ### Claim 17 An integrated circuit, comprising: a programmable logic block, comprising, a logic circuit, comprising: a first input node operable to receive a first stream of data values; a second input node operable to receive a second stream of data values; and a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output. ### Claim 18 An electronic system, comprising: an integrated circuit, comprising, a programmable logic block, comprising, a logic circuit, comprising, a first input node operable to receive a first stream of data values; a second input node operable to receive a second stream of data values; and a programmable logic circuit coupled to the first and second input nodes and operable in a dual-edge-triggered mode to store a first data value on the first input node in response to an edge of a clock signal and to store a second data value on the first input node in response to an opposite edge of the clock signal, the stored first and second data values being sequentially provided on a first output, and the logic circuit operable in a single-edge-triggered mode to store the first data value on the first input node in response to the edge of the clock signal and to provide the stored value on the first output and operable to store the second data value on the second input node in response to the edge of the clock signal and to provide the stored value on a second output. ### Claim 19 A method, comprising: during a first operational mode, storing a first data value from a first input signal in response to a first clock edge having a first polarity; and during the first operational mode, storing a second data value from the first input signal in response to a second clock edge having a second polarity that is opposite to the first polarity; during a second operational mode, storing a first data value from a first input signal in response to the first clock edge having a first polarity; and during the second operational mode, storing a second data value from a second input signal in response to the first clock edge having the first polarity. ### Claim 20 (depends on 19) The method of claim 19, further comprising: during the first operational mode, driving the stored first data value onto a first output node in response to the first clock edge; and during the first operational mode, driving the stored second data value onto the first output node in response to the second clock edge. ### Claim 21 (depends on 19) The method of claim 19, further comprising: during a second operational mode, storing a data value from the first input signal in response to a clock edge having the first polarity; and during the second operational mode, storing a data value from a second input signal in response to a clock edge having the second polarity. ### Claim 22 (depends on 19) The method of claim 19 wherein the first operational mode comprises a reduced-power mode.