Multiple-bit magnetic random access memory cell employing adiabatic switching
AssigneeInternational Business Machines Corporation
InventorYu Lu
Life of this patent
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Abstract
A multiple-bit memory cell for use in a magnetic random access memory circuit includes a first adiabatic switching storage element having a first anisotropy axis associated therewith and a second adiabatic switching storage element having a second anisotropy axis associated therewith. The first and second anisotropy axes are oriented at a substantially non-zero angle relative to at least one bit line and at least one word line corresponding to the memory cell. The memory cell is configured such that two quadrants of a write plane not used for writing one of the storage elements can be beneficially utilized to write the other storage element so that there is essentially no loss of write margin in the memory cell.
Claims22
A multiple-bit memory cell for use in a magnetic random access memory (MRAM) circuit, the MRAM circuit including at least one bit line and at least one word line corresponding to the memory cell, the memory cell comprising:
- a first adiabatic switching storage element having a first anisotropy axis associated therewith;
- and
- a second adiabatic switching storage element having a second anisotropy axis associated therewith, the first and second anisotropy axes being oriented at a substantially non-zero angle relative to the at least one bit line and the at least one word line corresponding to the memory cell.
A magnetic random access memory (MRAM) array including a plurality of multiple-bit memory cells and a plurality of bit lines and word lines for selectively accessing one or more of the memory cells, at least one of the memory cells comprising:
- a first adiabatic switching storage element having a first anisotropy axis associated therewith;
- and
- a second adiabatic switching storage element having a second anisotropy axis associated therewith, the first and second anisotropy axes being oriented at a substantially non-zero angle relative to at least one of the bit lines and at least one of the word lines corresponding to the at least one memory cell.
An integrated circuit including at least one multiple-bit memory cell, the at least one memory cell comprising:
- a first adiabatic switching storage element having a first anisotropy axis associated therewith;
- and
- a second adiabatic switching storage element having a second anisotropy axis associated therewith, the first and second anisotropy axes being oriented at a substantially non-zero angle relative to at least one bit line and at least one word line corresponding to the at least one memory cell.
Dependencies are inferred from the claim text.