In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development

A method for determination of tunnel oxide weakness, comprising:

• forming a tunnel oxide layer on a semiconductor wafer;
• forming at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer;
• forming at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell;
• performing a voltage contrast measurement on the voltage contrast tunnel oxide cell in a tester;
• generating and extracting test results from the tester;
• comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells in an analysis block;
• and
• determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons.

A system for determination of tunnel oxide weakness, comprising:

• a semiconductor wafer having at least one flash memory region and at least one voltage contrast cell region;
• a tunnel oxide layer on the semiconductor wafer;
• at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer;
• at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell;
• means for performing a voltage contrast measurement on the voltage contrast tunnel oxide cell;
• means for comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells;
• and
• means for determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons.

A system for determination of tunnel oxide weakness, comprising:

• a semiconductor wafer having at least one flash memory region and at least one voltage contrast cell region;
• a tunnel oxide layer on the semiconductor wafer;
• at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer;
• at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell;
• means for performing a voltage contrast measurement on the voltage contrast tunnel oxide cell in a tester;
• means for generating and extracting test results from the tester;
• means for comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells in an analysis block;
• and
• means for determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons.