Clock distribution device and method in compact PCI based multi-processing system
AssigneeLG Electronics Inc.
InventorSang Ik Jeong
Life of this patent
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Abstract
Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.
Claims16
A clock distribution device in a compact peripheral component interconnect (PCI) based multi-processing system comprising:
- a clock transmission device configured to transmit at least one clock between a first and second slot;
- and
- a clock driver configured to check whether the first slot is a system slot, the clock driver to generate a plurality of generated clocks, the clock driver to supply one of the generated clocks to the second slot, and to utilize one of the generated clocks for internal use if the first slot is the system slot, and the clock driver to block the generated clocks and to output a clock supplied from a system slot as a clock to be used internally if the first slot is not a system slots,
- wherein the clock driver comprises:
- a clock generator configured to generate a first clock signal,
- a clock distributor configured to distribute the first clock signal supplied from the clock generator into a plurality of second clock signals and output the plurality of second clock signals,
- a plurality of variable delay lines configured to delay and transmit the plurality of second clock signals though the plurality of variable delay lines of which a delay length may vary,
- a first buffer configured to switch at least one output of the plurality of second clocks to the second slot,
- a second buffer configured to store and output one of the plurality of second clock signals as a delay line for internal use,
- a multiplexer configured to select one of the plurality of second clock signals supplied from the second buffer and at least one clock supplied from an external system slot and the multiplexer to output the selected clock to be used internally within a multiplexer board, and
- a clock driver configuration logic configured to determine whether a clock driver board is mounted on a system board based upon an address signal and a slot enumeration signal of a higher-rank slot and the clock driver configuration logic to control operations of the variable delay lines, the first and second buffer, and the multiplexer.
A clock distribution method in a compact Peripheral Component Interconnect (PCI) based multi-processing system, comprising:
- configuring, at a board mounted on a system slot, a first delay line corresponding to a location of the system slot;
- transmitting a clock signal generated at the board mounted on the system slot to a peripheral slot through the first delay line;
- receiving, at a board mounted on the peripheral slot, clock signals transmitted from the system slot;
- and
- selecting and using, at the board mounted on the peripheral slot, the clock signal received from the system slot as a system slot internal clock.
A method of clock distribution in a compact Peripheral Component Interconnect (PCI) based multi-processing system, comprising:
- generating a first clock signal;
- distributing the first clock signal into a plurality of second clock signals;
- outputting each of the plurality of second clock signals through a corresponding variable delay line of a plurality of variable delay lines;
- switching an output of at least one of the plurality of second clock signals to a first and second slot using a first buffer;
- buffering and outputting the output of one of the plurality of second clock signals, using a second buffer, and specifying one of the plurality of second clock signals as an internal use clock.
A clock driver for a compact Peripheral Component Interconnect (PCI), comprising:
- a clock generator configured to generate a first clock signal;
- a clock distributor configured to distribute the first clock signal supplied from the clock generator into a plurality of second clock signals and output the plurality of second clock signals;
- a plurality of variable delay lines configured to delay and transmit the plurality of second clock signals through the plurality of variable delay lines of which the delay length may vary;
- a first buffer configured to switch at least one of the plurality of second clocks to a first and second slot;
- a second buffer configured to store and output one of the plurality of second clock signals as a delay line for internal use of the first clock signal;
- a multiplexer configured to select one of the plurality of second clock signals supplied from the second buffer and at least one of the plurality of the second clocks supplied from an external system slot and the multiplexer to output a selected clock to be used internally within a board having the multiplexer;
- and
- a clock driver configuration logic configured to determine whether a clock driver board is mounted on a system board based upon an address signal and a slot enumeration signal of a higher-rank slot and the clock driver configuration logic to control operations of the variable delay lines, the first and second buffer, and the multiplexer, wherein the clock driver is configured to check whether a first slot is a system slot, the clock driver further to supply a second slot generated clock to the second slot if the first slot is the system slot, and the clock driver to provide the second slot generated clock for the second clock's internal use if the first slot is not the system slot.
Dependencies are inferred from the claim text.