US 7,100,020 B1Granted

Digital communications processor

AssigneeFreescale Semiconductor, Inc.

InventorsThomas B. Brightman, Andrew T. Brown, John F. Brown, James A. Farrell, Andrew D. Funk, David J. Husak, Edward J. McLellan, Mark A. Sankey, Paul Schmitt, Donald A. Priore

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Abstract

An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Claims9

Dependent claims

An integrated circuit comprising:

a plurality of data stream inputs and/or outputs that receive and/or transmit streams of data;
a plurality of data stream processors that process the streams of data, each data stream processor is programmable and being coupled to a data stream input and/or data stream output and each data stream processor processing a stream of data from the data stream input and/or output, the data stream processor is coupled to as the data stream is received from the data stream input and/or transmitted to the data stream output, each data stream processor including:
a writeable instruction memory containing instructions, and
a control data processor that controls the data stream processor by sequentially executing instructions from the writeable instruction memory;
and
the integrated circuit further comprising:
an aggregator to perform receive aggregation to certain of the data stream processors that receive a data stream and to perform transmit aggregation to certain of the data stream processors that transmit a data stream, so that the aggregated data stream processors cooperate in processing a stream of data;
a context processor that responds to information received from a given data stream processor that is processing a data stream to produce information about the given data stream's context and provide the context information to the given data stream processor;
the given data stream processor using the context information to process the data stream;
and
wherein the integrated circuit being constructed on one chip.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/674,864Filed 7 May 1999 · us provisional application
Priority: 8 May 1998
Granted: 29 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H04L 49/10
Packet switching elements: characterised by the switching fabric construction
H04L 49/254
Using establishment or release of connections between ports: centralised controller, i.e. arbitration or scheduling
H04L 49/3009
Peripheral units, e.g. input or output ports: header conversion, routing tables or routing tags
H04L 49/3036
Peripheral units, e.g. input or output ports: shared queuing