Clock data recovery with selectable phase control

A method of controlling an integrated circuit, the method comprising:

• outputting a first command to the integrated circuit to set a first clock data recovery (CDR) circuit within the integrated circuit to a first mode, the first CDR circuit including a select circuit to select a first control signal to adjust the phase of a first clock signal when the first CDR circuit is in the first mode;
• delaying for a first time interval;
• and
• outputting, after the first time interval, a second command to the integrated circuit to set the first CDR circuit to a second mode, the select circuit of the first CDR circuit to select a second control signal when the first CDR circuit is in the second mode, the second control signal being generated by a second CDR circuit.

A system comprising:

• a first signal line;
• a receive device coupled to the first signal line, the receive device having a first clock data recovery (CDR) circuit to recover clock and data signals from the first signal line, the first CDR circuit including a control circuit, a select circuit and a phase adjust circuit, the control circuit to generate a first control signal according to a phase relationship between an input signal on the first signal line and a first clock signal, the select circuit being responsive to a first mode value to select from one of the first control signal and a second control signal to be output as a selected control signal, the phase adjust circuit to adjust the phase of the first clock signal according to the selected control signal;
• a control device coupled to the receive device to provide the first mode value;
• and
• at least one additional signal line, the at least one additional signal line coupled to the receive device and to the control device, the control device provides the first mode value to the receive device via the at least one additional signal line.

A system comprising:

• a first signal line;
• a receive device coupled to the first signal line, the receive device having a first clock data recovery (CDR) circuit to recover clock and data signals from the first signal line, the first CDR circuit including a control circuit, a select circuit and a phase adjust circuit, the control circuit to generate a first control signal according to a phase relationship between an input signal on the first signal line and a first clock signal, the select circuit being responsive to a first mode value to select from one of the first control signal and a second control signal to be output as a selected control signal, the phase adjust circuit to adjust the phase of the first clock signal according to the selected control signal;
• a control device coupled to the receive device to provide the first mode value;
• wherein the control device outputs the first mode value to the receive device and then, after a first time interval, outputs a second mode value to the receive device, the select circuit being responsive to the first mode value to select the first control signal to be output as the selected control signal, the select circuit being responsive to the second mode value to select the second control signal to be output as the selected control signal;
• and
• a second signal line coupled to the receive device, and wherein the receive device includes a second CDR circuit to recover clock and data signals from the second signal line, the second CDR circuit including a control circuit to generate the second control signal according to a phase relationship between an input signal on the second signal line and a second clock signal.

A method of testing an integrated circuit (IC) that includes a clock data recovery (CDR) circuit and a phase control port, the method comprising:

• outputting a command to the IC to set the CDR circuit to a mode of operation, the CDR circuit having a select circuit that responds to the mode of operation by selecting the phase control port to source a control signal instead of a phase control circuit within the CDR circuit, the control signal used by a phase adjust circuit within the CDR circuit to adjust the phase of a clock signal;
• outputting a phase control signal to the phase control port of the integrated circuit device to adjust the phase of the clock signal;
• and
• wherein outputting the first command to the integrated circuit to set the CDR circuit to the mode of operation comprises outputting a command to the integrated circuit to store a mode value in a programmable register within the integrated circuit, the mode value indicating the mode of operation.

A method of testing an integrated circuit (IC) that includes a clock data recovery (CDR) circuit and a phase control port, the method comprising:

• outputting a command to the IC to set the CDR circuit to a mode of operation, the CDR circuit having a select circuit that responds to the mode of operation by selecting the phase control port to source a control signal instead of a phase control circuit within the CDR circuit, the control signal used by a phase adjust circuit within the CDR circuit to adjust the phase of a clock signal;
• asserting a phase control signal at the phase control port of the integrated circuit for a first predetermined time interval, the phase adjust circuit within the CDR circuit responsive to the phase control signal to adjust the phase of the clock signal;
• deasserting the phase control signal for a second predetermined time interval;
• and
• measuring the clock signal with a signal measuring device while repeating asserting a phase control signal and deasserting the phase control signal at least until the phase of the clock signal has progressed through a predetermined portion of a cycle of the clock signal.

A method of testing an integrated circuit that includes a clock data recovery (CDR) circuit and a phase control port, the method comprising:

• setting the CDR circuit to a test mode in which a select circuit within the CDR circuit selects the phase control port to source a control signal instead of a phase control circuit within the CDR circuit, the control signal used by a phase adjust circuit within the CDR circuit to adjust the phase of a first clock signal;
• inputting a test signal to a receiver of the CDR circuit;
• comparing the test signal against samples of the test signal generated by the CDR circuit;
• asserting an error signal when the test signal does not match the samples;
• asserting a phase control signal at the phase control port to adjust the phase of the first clock signal;
• and
• repeating comparing the test signal, asserting an error signal and asserting a phase control signal to determine a maximum phase and a minimum phase of the first clock signal for which the error signal is not asserted.