Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure

A method for implementing thread replacement for optimal performance in a two-tiered multithreading structure comprising:

• utilizing first-tier state storage logic optimized for the high clock rate, storing a limited number of runnable thread register states;
• utilizing a second tier storage facility, storing state and predefined selection data for a second number of thread states including storing said predefined selection data including processor cycle usage efficiency data for each specific thread;
• said processor cycle usage efficiency data including a ratio of latency events per processor cycle, where a higher ratio indicates more inefficiency of a historical thread use of a processor;
• said second number of thread states being greater then said limited number of runnable thread register states and equal to all threads to run on a processor;
• said predefined selection data including predefined historical thread usage data;
• and
• utilizing runnable thread selection logic, processing said stored predefined selection data for each of said threads;
• and selectively exchanging thread states between said first tier state storage logic and said second tier storage facility based upon said predefined selection data.