Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation

A computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, the computer system having computer readable code which when executed by the computer system cause the computer system to implement a method for invalidating translated host instructions, comprising:

• translating a plurality of target instructions into a resulting plurality of host instructions;
• subsequent to translating target instructions at a memory location, testing whether the target instructions at the memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location;
• if the testing is slowing the computer system, initiating a checking process comprising:
• storing a copy of the target instructions;
• subsequently comparing the copy of the target instructions with the target instructions at the memory location;
• and
• invalidating the host instructions if the target instructions have changed.

In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes, comprising:

• subsequent to translating a sequence of target instructions at a memory location, testing whether the sequence of target instructions at the memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location;
• determining whether the testing is slowing the operation of the computer system;
• if the testing is slowing the operation of the computer system, initiating a checking process comprising:
• storing a copy of the sequence of target instructions at the memory location;
• subsequently comparing the copy with the sequence of target instructions at the memory location;
• and
• invalidating the host instructions if the sequence of target instructions has been altered.