Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout
AssigneeSun Microsystems, Inc.
InventorsMu-Jing Li, Suryanarayana R. Maturi, Pankaj Dixit
Life of this patent
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Abstract
An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.
Claims43
A method for use with a design layout, said method comprising the steps of:
- creating a patch cell for a given cell of the layout, said patch cell including at least some features from higher level cells above the given cell, and further including at least some features from the given cell;
- identifying layout errors in the patch cell;
- adding features to the patch cell to correct one or more of the identified errors;
- removing all but the added features from the patch cell;
- and then
- instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout.
A method for correcting an existing design layout, said method comprising the steps of:
- creating a patch cell for a cluster cell of the layout, said patch cell including covering metal features from higher level cells above the cluster cell, and further including metal and via features from the cluster cell;
- identifying isolated vias in the patch cell layout;
- adding dummy metal features to the patch cell within landing areas containing one or more identified isolated vias;
- then
- identifying remaining isolated vias in the patch cell layout;
- adding via fill arrays within landing areas containing one or more identified isolated vias;
- removing all but the added features from the patch cell;
- flagging any identified isolated vias which remain uncorrected;
- and then
- instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout.
A method of making a computer readable media product that encodes a design file representation of a design layout of an electronic circuit, said method comprising the steps of:
- creating a patch cell for a given cell of the layout, said patch cell including at least some features from higher level cells above the given cell, and further including at least some features from the given cell;
- identifying layout errors in the patch cell;
- adding features to the patch cell to correct one or more of the identified errors;
- removing all but the added features from the patch cell;
- and then
- instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout;
- and
- encoding the design layout into a computer readable medium.
A computer readable encoding of an electronic circuit design, the computer readable encoding comprising:
- one or more design file media encoding representations of a design layout for the electronic circuit design;
- wherein the computer readable encoding of the electronic circuit design was generated by the steps of:
- creating a patch cell for a given cell of the layout, said patch cell including at least some features from higher level cells above the given cell, and further including at least some features from the given cell;
- identifying layout errors in the patch cell;
- adding features to the patch cell to correct one or more of the identified errors;
- removing all but the added features from the patch cell;
- and then
- instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout.
An apparatus for processing one or more design files for an electronic circuit, the one or more design files encoding representations of a design layout of the electronic circuit, said design layout having vias connecting geometries of a first layer to geometries of a second layer, said apparatus comprising:
- means for creating a patch cell for a given cell of the layout, said patch cell including at least some features from higher level cells above the given cell, and further including at least some features from the given cell;
- means for identifying layout errors in the patch cell;
- means for adding features to the patch cell to correct one or more of the identified errors;
- means for removing all but the added features from the patch cell;
- and
- means for instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout.
A computer readable encoding of instructions for a computer, said instructions encoding a method for use with a design layout, for identifying and correcting layout errors within the design layout, said encoded method comprising the steps of:
- creating a patch cell for a given cell of the layout, said patch cell including at least some features from higher level cells above the given cell, and further including at least some features from the given cell;
- identifying layout errors in the patch cell;
- adding features to the patch cell to correct one or more of the identified errors;
- removing all but the added features from the patch cell;
- and then
- instantiating the patch cell into the layout to thereby effectuate the patch cell corrections into the layout.
Dependencies are inferred from the claim text.