Hierarchical semiconductor design
AssigneeMicron Technology, Inc.
InventorJoseph J. Karniewicz
Life of this patent
Estimating the term…
Abstract
Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.
Claims15
Apparatus comprising:
- a basic atom cell utilizable in design of a semiconductor test structure, the atom cell including:
- an underlayer geometry;
- a plurality of contacts arrayed into a contact block and aligned of the underlayer geometry;
- a plurality of metal caps, each cap placed over a corresponding contact;
- and,
- a metal pad globally covering one or more of the plurality of contacts.
A basic atom cell utilizable in design of a semiconductor test structure comprising:
- an underlayer geometry;
- a plurality of contacts arrayed into a contact block and aligned of the underlayer geometry;
- a plurality of metal caps, each cap placed over a corresponding contact;
- a metal pad globally covering one or more of the plurality of contacts;
- a hierarchy of abstractions ordered from highest to lowest, each abstraction relating a plurality of instances of an immediately lower abstraction, the highest abstraction corresponding to the structure, and the lowest abstraction corresponding to the basic atom;
- and
- a plurality of sets of parameters, each set of parameters corresponding to an instance of an abstraction, such that changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction, the plurality of sets of programmable parameters providing for control over relationship among the underlayer geometry, the plurality of contacts, the plurality of metal caps, and the metal pad.
A basic atom cell utilizable in design of a semiconductor structure comprising:
- a plurality of contacts arrayed into a contact block aligned in accordance with an underlayer geometry;
- a plurality of metal caps, at least one of the caps placed over a corresponding contact;
- a metal pad globally covering one or more of the plurality of contacts;
- a hierarchy of abstractions ordered from highest to lowest, each abstraction relating a plurality of instances of an immediately lower abstraction, the highest abstraction corresponding to the structure, and the lowest abstraction corresponding to the basic atom;
- and
- a plurality of sets of parameters, each set of parameters corresponding to an instance of an abstraction, such tat changing parameters for an instance changes parameters for an instance of an immediately lower abstraction, the parameters providing for control over a relationship among the plurality of contacts, the plurality of metal caps, and the metal pad.
Dependencies are inferred from the claim text.