Method for power consumption reduction
AssigneeIntel Corporation
InventorsJames W. Tschanz, Nasser A. Kurd, Javed Barkatullah, Vivek K. De
Life of this patent
Estimating the term…
Abstract
A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
Claims24
A chip design method comprising:
- providing a first functional block having a phase logic circuit in a first area of a chip design, the phase logic circuit including circuitry that depends on a phase or a voltage level of a clock signal;
- providing a second functional block having an edge-triggered circuit in a second area of the chip design;
- and
- replacing the edge-triggered circuit within the second functional block of the chip design with a dual edge-triggered circuit;
- providing a first clock signal in the chip design to clock the phase logic circuit;
- and
- providing a second clock signal in the chip design to clock the dual edge-triggered circuit, the second clock signal being different than the first clock signal.
A chip design method comprising:
- arranging a chip design such that a first functional block having a phase logic circuit is provided in a first area of a chip and a second functional block having a dual edge-triggered circuit is provided in a second area of the chip, the phase logic circuit being a circuit that depends on a phase or a voltage level of a clock signal, the first functional block being different than the second functional block;
- and
- arranging the chip design such that a first clock signal is distributed to said first functional block and a second clock signal is distributed to the dual edge-triggered circuit, the second clock signal being different than the first clock signal.
A method of designing a chip comprising:
- providing phase logic circuits in a first functional block of a chip design;
- providing single edge-triggered circuits in a second functional block of the chip design;
- replacing the single edge-triggered circuits in the second functional block with dual edge-triggered circuits in the second functional block of the chip design;
- and
- arranging the chip design to supply a first clock signal to the phase logic circuits and a second clock signal to the dual edge-triggered circuits, the second clock signal being based on the first clock signal.
Dependencies are inferred from the claim text.