US 7,096,413 B2Granted

Decomposer for parallel turbo decoding, process and integrated circuit

AssigneeLSI Logic Corporation

InventorsAlexander E. Andreev, Ranko Scepanovic, Vojislav Vukovic

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Abstract

A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.

Claims16

Dependent claims

A process of decomposing a set of parallel concatenated convolutional codes to select an address of an addressable location in each of a plurality of memories of up to n memories so that the selected addressable locations can be accessed in parallel, comprising steps of:

a) providing a function matrix and first and second matrices implemented at least in part in an integrated circuit, the function matrix having unique coordinates containing addresses of the addressable locations in the memories;
b) sorting a set of addresses of addressable locations into unique coordinate locations of the first and second matrices, each having m rows and n columns, such that each row contains no more than one address of a location in any one memory;
c) creating third and fourth matrices at least in part in the integrated circuit, each having m rows and n columns, the third and fourth matrices containing entries identifying coordinates of addresses in the function matrix, the entries being arranged at unique coordinate locations in the third and fourth matrices so that each entry in the third matrix is at coordinates that match coordinates in the first matrix containing an address, and each entry in the fourth matrix is at coordinates that match coordinates in the second matrix containing an address;
and
d) decoding the set of convolutional codes using the function, first, second, third and fourth matrices to select an address of an addressable location in each of the plurality of memories.

2 more elements

An integrated circuit containing a turbo decoder for selecting an address of an addressable location in each of a plurality of memories of up to n memories so that the selected addressable locations can be accessed in parallel, the turbo decoder comprising:

apparatus implemented at least in part in the integrated circuit and defining a function matrix having unique coordinates containing addresses of the addressable locations in the memories;
a decomposer in the integrated circuit for decomposing at least a set of parallel concatenated convolutional codes, the decomposer comprising:
apparatus implemented at least in part in the integrated circuit and defining first and second matrices, each having m rows and n columns,
sorting apparatus in the integrated circuit for sorting a set of addresses of addressable locations to unique coordinate locations in the first and second matrices such that each row of the first and second matrices contains no more than one address of a location in any one memory, and
apparatus implemented at least in part in the integrated circuit and defining third and fourth matrices, each having m rows and n columns, and containing entries identifying coordinates of addresses in the function matrix and arranged so that each entry in the third matrix is at coordinates that match coordinates in the first matrix containing an address, and each entry in the fourth matrix is at coordinates that match coordinates in the second matrix containing an address;
and
decoder apparatus in the integrated circuit responsive to entries in the function, first, second, third and fourth matrices for decomposing the convolutional codes to select an address of an addressable location in each of the plurality of memories.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/299,270Filed 19 Nov 2002
Published: US 2004/0098653 A120 May 2004
Granted: 22 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03M 13/6505
Reduction of hardware complexity or efficient processing: memory efficient implementations
H03M 13/2957
Combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes: turbo…
H03M 13/6566
Purpose and implementation aspects: implementations concerning memory access contentions
H03M 13/27
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability…:…