Memory controller for multilevel cell memory

A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer grater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:

• a common ECC circuit, which receives, in order, first through Mth (where M is greater than or equal to n) data groups, separated in an address direction, for the data groups of a first data bus connected to said host, and generates first through Mth error correction codes for correcting a single-bit defect for the respective first through Mth data groups, a gage of data being comprised of the first through Mth data groups;
• an error correction code holding unit, which holds said first through (M−1)th error correction codes;
• and,
• a data output unit, which outputs the first through Mth data groups to a second data bus connected to said N-level cell memory, such that n-data bits associated with one N-level cell are separated into first through Mth data groups, without overlap, such that each of the first through h Mth data groups include no more than a single one of the n data bits, wherein
• said data output unit outputs to said second data bus the first through (M−1)th error correction codes held by said error correction code holding unit, and the Mth error correction code generated by said ECC circuit.

A memory controller for a multilevel cell memory, connected between a host and an N-level (N=2n, where n is an integer greater than or equal to 2) cell memory, via data buses each with a plurality of bits, comprising:

• first through Mth ECC circuits, which receive first through Mth (where M is greater than or equal to n) data groups, separated in an address direction, for the data groups of a first data bus connected to said host, and generate first through Mth error correction codes for correcting a single-bit defect for the respective first through Mth data groups, a page of data being comprised of the first through Mth data groups;
• and,
• a data output unit, which outputs the first through Mth data groups to a second data bus connected to said N-level cell memory, such that n data bits associated with one N-level cell are separated into first through Mth data groups, without overlap, such that each of the first through Mth data groups include no more than a single one of the n data bits, wherein
• said data output unit further outputs to said second data bus the respective error correction codes generated by said first through Mth ECC circuits.