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US 7,096,398 B1Granted
Distributed test control architecture
AssigneeIntel Corporation
InventorAditya Mukherjee
Life of this patent
Estimating the term…
Abstract
The invention includes an integrated circuit. The integrated circuit includes a test controller, at least one logic unit controller, and a test bus connected between the test controller and the logic unit controller. A design for test feature is connected to the logic unit controller. Moreover, a logic unit can be connected to the design for test feature.
Claims24
An integrated circuit comprising:
- a test controller;
- a logic unit controller of the integrated circuit;
- a single test bus of the integrated circuit, the single test bus coupled between the test controller and the logic unit controller;
- a plurality of design for test features of the integrated circuit, the design for test features coupled to the logic unit controller;
- and
- a logic unit of the integrated circuit, the logic unit coupled to the logic unit controller and to the design for test features,
- wherein the test controller is to provide a global control signal as a packet including a plurality of different types of instruction signals to the logic unit controller over the single test bus, wherein the logic unit controller is to receive the packet and provide a plurality of different types of instruction signals to a design for test feature.
4 more elements
A platform comprising:
- a support structure;
- a processor, a memory controller, a memory chip, and a graphics controller each disposed on and coupled with the support structure;
- and
- an integrated circuit to be tested that is disposed on and coupled with the support structure, the integrated circuit including:
- a test controller;
- a logic unit controller;
- a single test bus coupled between the test controller and the logic unit controller;
- a plurality of design for test features coupled to the logic unit controller;
- and
- a logic unit coupled to the logic unit controller and to the design for test features,
- wherein the test controller is to provide a global control signal as a packet including a plurality of different types of instruction signals to the logic unit controller over the single test bus, wherein the logic unit controller is to receive the packet and provide a plurality of different types of instruction signals to a design for test feature.
8 more elements
A method comprising:
- generating a test information packet in a test controller of an integrated circuit;
- transmitting the test information packet to a logic unit controller of the integrated circuit over a single test bus coupled between the test controller and the logic unit controller;
- processing the test information packet within the at least one logic unit controller to generate a local shift signal and a local load signal;
- and
- transmitting the local shift signal and the local load signal to a design-for-test-feature.
2 more elements
Dependencies are inferred from the claim text.