Dft technique for avoiding contention/conflict in logic built-in self-test

#This invention relates generally to integrated circuit devices, and more particularly, to testing of semiconductor integrated circuit devices.

#Testing an integrated circuit device or a packaged component including circuitry (generally referred to as a device under test (DUT)) at the time it is manufactured and before it is incorporated into a next level assembly is generally necessary to ascertain the functionality of the DUT. A microprocessor, for instance, should be tested before it is incorporated into a next level assembly to avoid the cost of discarding the whole assembly, or to avoid a costly diagnosis and repair after it is assembled into the next level assembly.

#Traditionally, microprocessors and integrated circuit devices have been subjected to functional testing using an external tester. These external testers contain a large memory that stores test data patterns of ones and zeros used as inputs to the microprocessor along with patterns of correct outputs expected from the microprocessor. The benefits of functional testing include testing the device in the native mode of operation, making speed testing easier, and providing collateral coverage of faults not modeled during the fault grading process. The drawback of functional testing is that the external tester performance has to keep up with microprocessor performance improvements, and the writing of test data patterns for functional testing can take as much as 60 to 100 man-years. Also, functional testing generally increases tester data volume and the application time require to develop the test methodology.

#FIG. 1 is a flow diagram of one embodiment the present invention.

#FIG. 2 is a block diagram including components of the embodiment shown in 5 FIG. 1.

#FIG. 3 illustrates major components of constraint correction and X-masking schemes implemented according to the present invention.

#In the following detailed description of the embodiments, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Moreover, it is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described in one embodiment may be included within other embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

#The present invention provides a method and apparatus for structurally testing DUTs to avoid the bus contention problems and the X-generation problems generally associated with BIST methodology of testing the integrated circuit devices. For one embodiment, a pattern generator, a programmable constraint correction module, a programmable X masking module, and a signature analyzer are all incorporated into an integrated circuit device to circumvent these problems.

#FIG. 1 is an exemplary flow chart 100 of structurally testing an integrated circuit device, also referred to as device under test (DUT) incorporated in a packaged component or a chip. In some embodiments, the integrated circuit device can include a microprocessor having an on-chip cache memory.