Built-in self-test (BIST) of memory interconnect

A built-in self-testing (BIST) system for testing a memory interconnect between an external memory module and a chip, the BIST system comprising:

• an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module;
• an on-chip BIST module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions;
• a multiplexer coupled to the instruction register to permit loop tests;
• and
• an interface controller coupled to the BIST module to provide an interface to access the BIST module,
• wherein once the external memory module has successfully passed the testing, the external memory module is utilized in testing the memory interconnect.

A built-in self-testing (BIST) system for testing a memory interconnect between an external memory module and a chip, the BIST system comprising:

• means for providing an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module;
• means for providing an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions;
• means for coupling a multiplexer to the instruction register to permit loop test;
• means for testing the external memory module;
• and
• once the external memory module has successfully passed the testing, means for utilizing the external memory module in testing the memory interconnect.