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US 7,096,375 B2Granted
Data transfer circuit between different clock regions
AssigneeFujitsu Limited
InventorsShigetoshi Wakayama, Hiroshi Okano, Yoshio Hirose
Life of this patent
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Abstract
A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.
Claims6
A circuit for data transfer, comprising:
- a selector circuit configured to receive data at a first clock frequency;
- a first buffer coupled to said selector circuit to store data supplied from said selector circuit by operating at the first clock frequency;
- and
- a plurality of second buffers coupled to said selector circuit to store data supplied from said selector circuit by operating at a second clock frequency,
- wherein said selector circuit is configured to select one of said first buffer and said second buffers successively to send the received data to the selected one of said first buffer and said second buffers.
2 more elements
Dependencies are inferred from the claim text.