System and method for optimizing clock speed generation in a computer

A method for performing clock speed generation, comprising:

• receiving a base clock signal;
• selectively multiplying the base clock signal by a first factor to produce a first higher frequency clock signal, and by a second factor to produce a second higher frequency clock signal, wherein the first and second higher frequency clock signals are different and phase-locked with the base clock signal;
• receiving a power mode signal;
• selectively outputting the first higher frequency clock signal to a first device and the second higher frequency clock signal to a second device based on the power mode signal, wherein the first device is a processor and the second device is a bridge controller;
• and
• generating a third higher frequency clock signal for a video processor, wherein the third clock signal being distinct from the first and second clock signals and having a different frequency than the first and second clock signals.

A method for performing clock speed generation, comprising:

• supplying a first clock signal by a first logic to generate a first higher frequency clock signal to a CPU;
• supplying a second clock signal by a second logic to generate a second higher frequency clock signal to a bridge controller, wherein the first and second clock signals are distinct;
• receiving by the second logic, a power mode signal and adjusting the second clock signal;
• and
• selectively outputting the second higher frequency clock signal based on the power mode signal independent of the first clock signal, wherein the bridge controller controls a clock speed of a bus connected therebetween for data communication with the CPU using the outputted second higher frequency clock signal.