US 7,096,349 B1 · Firmware algorithm for initializing memory modules for optimum performance

Abstract

A technique for initializing a memory controller of a plurality of memory modules for optimum system performance is presented. A plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules are determined. A plurality of benchmark calculations using the plurality of optimum sets of operational parameters produces a plurality of benchmark numbers. The memory controller is configured with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers. The benchmark calculations can be based on a variety of conditions, for example, burst length or the minimum time to read a random row of memory. Additionally, the benchmark calculations can be weighted in favor of frequency.

Claims46

Dependent claims

A method for initializing a memory controller of a plurality of memory modules comprising:

determining a plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules;
performing a plurality of benchmark calculations using the plurality of optimum sets of operational parameters producing a plurality of benchmark numbers;
and
programming the memory controller with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers;
wherein the determining the plurality of optimum sets of operational parameters comprises:
selecting a cycle time/CAS latency parameter pair;
and
determining if the memory controller and each of the plurality of memory modules supports the cycle time/CAS latency parameter pair;
if any of the plurality of memory modules or the memory controller does not support the cycle time/CAS latency parameter pair, selecting another cycle time/CAS latency parameter pair and repeating the determining and the selecting until a supported cycle time/CAS latency parameter pair are found.

6 more elements

A computer program product for initializing a memory controller of a plurality of memory modules comprising:

a set of software instructions stored on computer readable media, the set of software instructions configured to:
determine a plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules;
perform a plurality of benchmark calculations using the plurality of optimum sets of operational parameters producing a plurality of benchmark numbers;
and
program the memory controller with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers;
wherein to determine the plurality of optimum sets of operational parameters the set of software instructions is configured to:
select a cycle time/CAS latency parameter pair;
and
determine if the memory controller and each of the plurality of memory modules supports the cycle time/CAS latency parameter pair;
if any of the plurality of memory modules or the memory controller does not support the cycle time/CAS latency parameter pair, select another cycle time/CAS latency parameter pair and repeat determining and selecting until a supported cycle time/CAS latency parameter pair are found.

7 more elements

An apparatus for initializing a memory controller of a plurality of memory modules comprising:

means for determining a plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules;
means for performing a plurality of benchmark calculations using the plurality of optimum sets of operational parameters producing a plurality of benchmark numbers;
means for programming the memory controller with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers;
wherein the means for determining the plurality of optimum sets of operational parameters comprises:
means for selecting a cycle time/CAS latency parameter pair;
and
means for determining if the memory controller and each of the plurality of memory modules supports the cycle time/CAS latency parameter pair;
means for selecting another cycle time/CAS latency parameter pair and repeating the means for determining and the means for selecting until a supported cycle time/CAS latency parameter pair are found if any of the plurality of memory modules or the memory controller does not support the cycle time/CAS latency parameter pair.

5 more elements

Dependencies are inferred from the claim text.

Firmware algorithm for initializing memory modules for optimum performance

Life of this patent

Firmware algorithm for initializing memory modules for optimum performance

Life of this patent

Abstract

Claims46