Microprocessor having instructions for exchanging values between two registers or two memory locations

A microprocessor comprising:

• a first internal register;
• an arithmetic and logic unit connected to said first internal register;
• a second internal register connected to an output of said arithmetic and logic unit;
• and
• means for reading instruction code stored in a program memory during a first clock cycle and for transferring the contents of the first internal register to said second internal register during said first clock cycle, said instruction code belonging to an instruction set of instructions executable by the microprocessor, the instruction set comprising at least one exchange instruction for exchanging contents between said first internal register and a memory location,
• means for executing said exchange instruction performing subsequent to reading an exchange instruction in the program memory during a first clock cycle of the microprocessor
• transferring the contents of the memory location to the first internal register during a successive second clock cycle, and
• transferring the contents of said second internal register to the memory location during a successive third clock cycle.

A method for operating a microprocessor for exchanging contents between first and second memory locations, the microprocessor comprising an arithmetic and logic unit and a first internal register connected to an output of the arithmetic and logic unit, the method comprising:

• reading a program memory and executing instructions read therein, the instructions belonging to a set of instructions executable by the microprocessor and comprising at least one exchange instruction for exchanging contents between first and second memory locations, and subsequent to reading an exchange instruction in the program memory during a first clock cycle
• transferring the contents of the first memory location to the first internal register during a successive second clock cycle;
• transferring the contents of the second memory location to the first memory location during a successive third clock cycle;
• and
• transferring the contents of the first internal register to the second memory location during a successive fourth clock cycle.