Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof

A data processing system for executing a plurality of instructions having a prescribed program order, the data processing system comprising:

• a register file means including a plurality of register means to store data;
• a buffering means including N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M>0;
• and
• a plurality of functional means, each functional means capable of executing instructions regardless of the prescribed program order, and
• wherein the buffering means temporarily stores data corresponding to the plurality of instructions and, when data of one of the plurality of instructions to be executed by a corresponding one of the plurality of functional means is temporarily stored in one of the M bypassable buffer locations, the data in one of the bypassable M buffer locations is transferred to the corresponding one of the functional means in order to execute the instruction, and
• wherein the register file means also stores data corresponding to retired ones of the plurality of instructions.

In a processor for executing a plurality of instructions having a prescribed program order, the processor comprising:

• a register file including a plurality of registers to store instruction data;
• a reorder buffer including N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M>0, wherein the reorder buffer temporarily stores data corresponding to the plurality of instructions;
• a plurality of execution units, each execution unit capable of executing instructions regardless of the prescribed program order, and
• an issue logic to issue data from the register file to one of the N buffer locations and, wherein when data of one of the plurality of instructions to be executed by a corresponding one of the plurality of execution units is temporarily stored in one of the M bypassable buffer locations, the issue logic transfers data stored or to be stored in one of the bypassable M buffer locations to the corresponding one of the execution units in order to execute the instruction.

In a processor for executing a plurality of instructions having a prescribed program order, the processor comprising:

• a register file means including a plurality of register means to store data;
• a buffering means including N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M>0, wherein the buffering means temporarily stores data corresponding to the plurality of instructions;
• a plurality of execution means, each execution means capable of executing instructions regardless of the prescribed program order, and
• an issue logic means to issue data from the register file means to one of the N buffer locations and, wherein when data of one of the plurality of instructions to be executed by a corresponding one of the plurality of execution means is temporarily stored in one of the M bypassable buffer locations, the issue logic means transfers data stored or to be stored in one of the bypassable M buffer locations to the corresponding one of the execution means in order to execute the instruction.

In a reorder buffer having a N buffer locations of which M buffer locations are bypassable and N−M buffer locations are non-bypassable, wherein N and M are integers and N>M>0, a method comprising:

• fetching one or more instructions;
• decoding one or more instructions;
• checking if a data hazard condition exists from one of the decoded instructions;
• if a data hazard condition exists, checking if data is available in one of the bypassable M buffer locations for executing one of the decoded instructions;
• and
• transferring the data if available in one of the bypassable M buffer locations to an execution unit for executing one of the decoded instructions.