Embedded processor with dual-port SRAM for programmable logic

A programmable logic integrated circuit comprising:

• a programmable logic portion comprising a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions;
• and
• an embedded processor portion coupled to the programmable logic portion and comprising:
• a processor;
• and
• a memory block coupled to the processor and comprising:
• a first plurality of memory cells for storing data;
• a second plurality of memory cells for storing data;
• a first port coupled to the first and second pluralities of memory cells;
• a second port coupled to the first and second pluralities of memory cells;
• and
• an arbiter coupled to the first port and the second port,
• wherein when the second port is accessing a subset of the first plurality of memory cells, the arbiter prevents the first port from accessing the first plurality of memory cells, and when the second port is accessing the subset of the first plurality of memory cells, the arbiter allows the first port to access the second plurality of memory cells.

An integrated circuit comprising:

• a programmable logic portion;
• and
• a memory block coupled to the programmable logic portion and comprising:
• a first plurality of memory cells for storing data;
• a second plurality of memory cells for storing data;
• a first port coupled to the first and second pluralities of memory cells;
• a second port coupled to the first and second pluralities of memory cells;
• and
• an arbiter coupled to the first port and the second port,
• wherein when the first port is accessing a subset of the first plurality of memory cells, the arbiter prevents the second port from accessing the first plurality of memory cells and allows the second port to access the second plurality of memory cells, and
• wherein the first plurality of memory cells consists of a number of memory cells and the number is configurable.