Shared write buffer in a peripheral interface and method of operating

A peripheral interface for interfacing a bus and a plurality of peripherals comprising:

• bus interface circuitry coupled to the bus to receive write accesses from the bus;
• peripheral interface circuitry for providing write access to the plurality of peripherals;
• a write buffer coupled to the bus interface circuitry and configured to receive write accesses from the bus interface circuitry and to provide write access to each of the plurality of peripherals via the peripheral interface circuitry;
• control logic coupled to the bus interface circuitry and the peripheral interface circuitry, the control logic controlling whether to release the bus prior to completing a write access to an addressed one of the plurality of peripherals based at least upon which peripheral is being accessed;
• and
• an input coupled to a receive a control signal from one or more of the plurality of peripherals, wherein a determination of whether to release the bus prior to completion of a write to the one or more of the plurality of peripherals is based upon the control signal.

A method for performing a write access to a peripheral of a plurality of peripherals comprising:

• receiving a write access to the peripheral of the plurality of peripherals from an initiator via a bus;
• determining whether to release the bus prior to completing the write access to the peripheral based at least upon which of the plurality of peripherals is being accessed and based upon which initiator of a plurality of initiators is initiating the write access;
• completing the write access to the peripheral;
• releasing the bus, wherein the bus is released either prior to completing the write access or after completing the write access based on the determining.

A peripheral interface comprising:

• input circuitry to receive write accesses from a bus;
• a peripheral bus controller to provide write access to a plurality of peripherals;
• and
• control logic configured to determine whether to release the bus prior to completion of a write access to a peripheral of the plurality of peripherals based at least upon which initiator of a plurality of initiators is initiating the write access.

A peripheral interface comprising:

• input circuitry to receive write accesses from a bus;
• peripheral interface circuitry to provide write access to a plurality of peripherals;
• and
• control logic configured to determine whether to release the bus prior to completing a write access to a peripheral of the plurality of peripherals based at least upon a mode of operation of a plurality of modes of a write access initiator.

A peripheral interface comprising:

• input circuitry to receive write accesses from a bus;
• peripheral interface circuitry to provide write access to a plurality of peripherals;
• and
• control logic coupled to the input circuitry, the control logic configured to determine whether to release the bus prior to completing a write access to a peripheral of the plurality of peripherals, wherein the control logic is responsive to an override control signal from the peripheral of the plurality of peripherals that overrides bus policy by being indicative of whether the bus is released prior to completion of the write access to the peripheral.