Apparatus and method for managing voltage buses
AssigneeMicron Technology, Inc.
InventorsDuc V. Ho, Scott E. Smith
Life of this patent
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Abstract
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply voltage to periphery circuitry and an array voltage bus may supply voltage to array circuitry. A bridge circuit may be utilized to isolate the buses from each other and couple the buses together, depending on the control signals are received by the bridge circuit. As such, the bridge circuit enhances the operation of the memory device by reducing duplicative circuits and equalizing the voltage that are applied to the buses. In addition, the bridge circuit isolates the buses from each other to protect sensitive circuitry in the array and periphery circuitry from noise on the other bus.
Claims40
A system comprising:
- a processor;
- and
- a memory device coupled to the processor that comprises:
- a first voltage bus;
- a second voltage bus;
- and
- a bridge circuit coupled between the first voltage bus and the second voltage bus,
- wherein the bridge circuit is adapted to:
- receive an input signal;
- connect the first voltage bus and the second voltage bus together if the input signal is a first control signal;
- and
- isolate the first voltage bus from the second voltage bus if the input signal is a second control signal.
A memory device comprising:
- a periphery voltage bus coupled to periphery circuitry;
- an array voltage bus coupled to array circuitry;
- and
- a bridge circuit coupled between the periphery voltage bus and the array voltage bus,
- wherein the bridge circuit is configured to:
- receive an input signal;
- connect the periphery voltage bus and the array voltage bus together if the input signal is a first control signal;
- and
- isolate the periphery voltage bus from the array voltage bus if the input signal is a second control signal.
A method of operating a device comprising the acts of:
- providing a first voltage to a periphery voltage bus and a second voltage to an array voltage bus;
- receiving a control signal at a bridge circuit;
- determining if the control signal indicates one of a first condition and a second condition;
- coupling the periphery voltage bus to the array voltage bus if the control signal indicates the first condition;
- and
- isolating the periphery voltage bus from the array voltage bus if the control signal indicates the second condition.
A method of manufacturing a memory device comprising the acts of:
- providing a memory device having a first voltage bus and a second voltage bus;
- coupling a power amplifier to one of the first voltage bus and the second voltage bus;
- coupling a bridge circuit to the first voltage bus and the second voltage bus;
- encoding the memory device to provide a first control signal that couples the first voltage bus to the second voltage bus in response to a first condition;
- and
- encoding the memory device to provide a second control signal that isolates the first voltage bus from the second voltage bus in response to a second condition.
Dependencies are inferred from the claim text.