Reduced cardbus controller
Assignee02Micro International Limited
InventorsNeil Morrow, Richard Brayden
Life of this patent
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Abstract
A cardbus controller is provided that reduces signal count and board area. In one exemplary embodiment, the controller is adapted to multiplex selected signals in a two PC Card system so that signal lines are not repeated. The selected signals may include common signals between two PC Cards. The controller may also include early detection circuitry, arbitration circuitry and power management circuitry to more effectively operate two PC Cards. In other exemplary embodiments, the invention provides a method of reducing the chip area of a PC Card controller integrated circuit by mapping an internal IDSEL signal to an external address line.
Claims5
A method of reducing the chip area of a PC Card controller integrated circuit, comprising:
- arranging a first power rail having a first voltage and a second power rail having a second voltage, each said power rail operable to supply power to PC Cards;
- grouping pins of said integrated circuit into a first group of pins and a second group of pins;
- coupling said first power rail with said first group of pins and coupling said second power rail with said second group of pins;
- and
- overlapping said first power rail only with said first group of pins and overlapping said second power rail only with said second group of pins.
A method of reducing the chip area of a PC Card controller integrated circuit, comprising the step of:
- sampling VCCD0 and VCCD1 signals, as defined by a PCI Specification, during a reset period of said integrated circuit to determine which address line to map a IDSEL signal;
- and
- mapping an internal IDSEL signal within said PC Card controller integrated circuit to an external address line of a bus.
Dependencies are inferred from the claim text.