Supercharge message exchanger
AssigneeEmulex Design & Manufacturing Corporation
InventorsMichael Liu, Bradley Roach, Sam Su, Peter Fiacco
Life of this patent
Estimating the term…
Abstract
A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
Claims10
A method comprising:
- receiving input/output (I/O) completions from a plurality of data paths, the plurality of data paths including first processor data paths for I/O completions resulting from I/O requests initiated by a first processor, and a write data path for I/O completions resulting from I/O requests initiated by a second processor;
- storing the I/O completions in a plurality of registers, each register being configured to store an I/O completion from one of the plurality of data paths;
- transferring the I/O completions from the plurality of registers to a plurality of logical blocks of a random access memory, each logical block being configured to store I/O completions from one of the plurality of data paths, wherein each respective register and each respective logical block are associated with a respective predetermined one of the plurality of data paths;
- and
- processing the I/O completions stored in the plurality of logical blocks using the first processor, including the I/O completions resulting from the I/O requests initiated by the second processor.
Dependencies are inferred from the claim text.