Architecture of reconfigurable radio processor

An architecture of reconfigurable radio processor applied to a platform having a main processor and on-chip bus, said architecture of reconfigurable radio processor comprising:

• a bus interface having a task dispatcher describing an application task from the platform, said bus interface configuring a task into a command zone and a data zone to be processed for forming a configuration;
• and
• an execution kernel including a global control unit, at least a function unit, a control network and a data network, each function unit having a local control unit for executing a local operation received from said global control unit, said local control unit having an operation interface and a data interface, wherein said operation interface works during a setting phase of said function unit and transfers control to said data interface after having completed the local operation and entering an execution phase of said function unit;
• wherein said global control unit decodes and executes basic operations that have to be done by said radio processor of different versions and transfers the local operation to a corresponding function unit via said control network, every function unit executes the local operation and processes data thereof in a corresponding task, and then, transfers the processed data to a next function unit for further processing via said data network.