Synchronous flash memory with status burst output
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.
Claims17
Amethod of operating a synchronous memory device comprising:
- establishing a read burst length of x-cycles in a mode register such that data output from a status register of the synchronous memory device is output on x-consecutive clock cycles;
- initiating a register read operation to read data stored in the status register;
- and
- outputting data stored in the status register on external data connections for x-consecutive clock cycles;
- wherein the mode register is used to define the specific operation of the synchronous memory device including selecting at least one of a burst length, a burst type, a CAS latency, and an operating mode, and wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.
Amethod of operating a synchronous memory device comprising:
- receiving a read status register command;
- and
- outputting status register data from the synchronous memory device in response to the read register command for x-clock cycles;
- wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.
Amethod of reading register data in a synchronous memory device comprising:
- providing a status register read command from a processor to the memory device;
- receiving the register read command on an input of the memory device on a first clock cycle;
- reading status register data stored in a memory register;
- outputting the status register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein outputting the status register data is delayed for a predefined clock latency period after receiving the register read command;
- wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.
Amethod of operating a synchronous memory device, comprising:
- programming a status read register with a burst length setting and clock latency setting;
- placing the memory in a status register read mode;
- and
- outputting non-array data from a status register for a series of clock cycles according to the read register programming;
- wherein the status register allows an external processor to monitor the status of an internal state machine during write, erase, and protect operations.
Dependencies are inferred from the claim text.