Flexible decimator
AssigneeZarlink Semiconductor Inc.
InventorsRobertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
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AssigneeZarlink Semiconductor Inc.
InventorsRobertus Laurentius Van Der Valk, Johannes Hermanus Aloysius De Rijk
Estimating the term…
A decimator for use in digital signal processing has an input line for receiving a sequence of input samples at a first sampling rate and a first register for accumulating input samples for which the order in the sequence is a power of a predetermined number greater than one. A control unit for outputs samples from the first register at a second sampling rate. Typically accumulates input samples for which the order in the sequence is a not power of the predetermined number so that the first register accumulates input samples for which the order of said sequence is a power of the predetermined number combined with a current accumulated value in the second register.
A decimator for use in digital signal processing comprising:
A method of decimating an input signal in the form of a sequence of input samples at a first sampling rate, comprising:
Dependencies are inferred from the claim text.
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The ratio being integer: where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
Measures concerning the multipliers: comprising look-up tables
Impedance networks
Term ended 14 Oct 2024 (estimated)
This invention relates to the field of digital signal processing, and more particularly to a decimator.
Digital filtering is employed in many areas, for example, in measurement systems, source coding, echo cancellation etc. A relatively common filter function is decimation.
A decimator is a structure that combines samples into a single sample. It typically consists of an electronic hardware structure (ASIC's, FPGA's and the like) or software (DSP's), and can be used in any environment where sampling is possible. The decimation function typically has two objectives, namely reduction of the number of samples and an increase in the accuracy of the samples.
The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:
FIG. 1 is a first embodiment of a prior art decimator;
FIG. 2 is a second embodiment of a prior art decimator;
The novel decimator is best explained first in mathematical equivalencies, since these show best illustrate the underlying principles of the invention. A normal decimator over M will perform the following operation:
Output ( N ) = ∑ i = 0 M - 1 Input ( N * M + i ) M
This means that the output process is M times slower than the input process, and that the output is the average of the last block of M samples.