Random number generator and generation method
OwnerScott A. Wilberinventor
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OwnerScott A. Wilberinventor
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An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.
A method of producing and utilizing a true random number, said method comprising:
A true random number generator system comprising:
A true random number generator system comprising:
A true random number generator system comprising:
A method of producing a series of high-quality true random numbers, said method comprising the steps of:
Dependencies are inferred from the claim text.