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US 7,096,177 B2Granted
Multiprocessor array
AssigneeKoninklijke Philips Electronics N.V.
InventorsAxel Hertwig, Rainer Mehling, Stephan Koch
Life of this patent
Estimating the term…
Abstract
A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.
Claims12
A multiprocessor array which includes:
- a) a first processor shadow register unit (1) which operates within a first clock domain and includes i) a first processor (2), and ii) a first shadow register unit (3) which is connected to the first processor (2) so as to transmit data bidirectionally, b) at least one second processor shadow register unit (9) which i) operates within a corresponding second clock domain, ii) includes a second processor (10), and iii) a second shadow register unit (11) which is connected to the second processor (10) so as to transmit data bidirectionally, and c) a peripheral unit (17) which operates within a peripheral clock domain and includes i) a multiplexer unit (18) which is connected to the first shadow register unit (3) and the at least one second shadow register unit (11) so as to transmit data bidirectionally, ii) a register unit (20) having the construction and identical function of the first shadow register unit (3) and the at least one second shadow register unit (11), and iii) a priority unit (19) directly connected to a multiplexer unit (18) via only a single action connection for applying control signals thereto and for allocating the multiplexer unit (18) for data transmission to the first shadow register unit (3) or to the at least one second shadow register unit (11) based on at least one criterion, the priority unit (19) being connected to the first shadow register unit (3) and to the at least one second shadow register unit (11), via a corresponding asynchronous request line, said request line informing the priority unit of changes in a corresponding shadow register.
A communication terminal using a multiprocessor array comprising:
- a) a first processor shadow register unit (1) which operates within a first clock domain and includes i) a first processor (2), and ii) a first shadow register unit (3) which is connected to the first processor (2) so as to transmit data bidirectionally, b) at least one second processor shadow register unit (9) which i) operates within a corresponding second clock domain, ii) includes a second processor (10), and iii) a second shadow register unit (11) which is connected to the second processor (10) so as to transmit data bidirectionally, and c) a peripheral unit (17) which operates within a peripheral clock domain and includes i) a multiplexer unit (18) which is connected to the first shadow register unit (3) and the at least one second shadow register unit (11) so as to transmit data bidirectionally, ii) a register unit (20) having the construction and identical function of the first shadow register unit (3) and the at least one second shadow register unit (11), and iii) a priority unit (19) directly connected to a multiplexer unit (18) via only a single active connection for applying control signals thereto and for allocating the multiplexer unit (18) for data transmission to the first shadow register unit (3) or to the at least one second shadow register unit (11) based on at least one criterion, the priority unit (19) being connected to the first shadow register unit (3) and to the at least one second shadow register unit (11), via a corresponding asynchronous request line, said request line informing the priority unit of changes in a corresponding shadow register.
A portable device using a multiprocessor array comprising:
- a) a first processor shadow register unit (1) which operates within a first clock domain and includes i) a first processor (2), and ii) a first shadow register unit (3) which is connected to the first processor (2) so as to transmit data bidirectionally, b) at least one second processor shadow register unit (9) which i) operates within a corresponding second clock domain, ii) includes a second processor (10), and iii) a second shadow register unit (11) which is connected to the second processor (10) so as to transmit data bidirectionally, and c) a peripheral unit (17) which operates within a peripheral clock domain and includes i) a multiplexer unit (18) which is connected to the first shadow register unit (3) and the at least one second shadow register unit (11) so as to transmit data bidirectionally, ii) a register unit (20) having the construction and identical function of the first shadow register unit (3) and the at least one second shadow register unit (11), and iii) a priority unit (19) directly connected to a multiplexer unit (18) via only a single active connection for applying control signals thereto and for allocating the multiplexer unit (18) for data transmission to the first shadow register unit (3) or to the at least one second shadow register unit (11) based on at least one criterion, the priority unit (19) being connected to the first shadow register unit (3) and to the at least one second shadow register unit (11), via a corresponding asynchronous request line, said request line informing the priority unit of changes in a corresponding shadow register.
Dependencies are inferred from the claim text.