Method for measuring registration of overlapping material layers of an integrated circuit
AssigneeMicron Technology, Inc.
InventorsEugene A. DeLaRosa, Troy V. Gugel
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Abstract
A method and apparatus for measuring registration between two or more integrated circuit layers is disclosed. Images of actual operative circuitry of different layers of a semiconductor wafer, obtained by an optical technique or a scanning electron microscope, are digitized and analyzed for the relative placement of pattern shapes of the corresponding layers. This relative placement is then compared to tolerance values and if out of tolerance misregistration of the two layers is indicated.
Claims36
A method for measuring the registration between at least two integrated circuit layers, one residing over the other, said method comprising:
- generating a top-down image of a field of said at least two integrated circuit layers, each of said layers having a respective visible feature in said image;
- digitizing said image and processing said digitized image to determine a relative location of said visible feature of one of said layers, relative to said visible feature of the other of said layers;
- determining a location of a first feature reference point in said visible feature of one of said layers, and a location of a second feature reference point in said visible feature of the other of said layers, to indicate a relative location, wherein at least one of said visible features is a non-metrological structure on said one of said integrated circuit layers;
- and
- determining if said relative location is within stored acceptable design limits for said integrated circuit layers by comparing said relative location to said stored acceptable design limits.
A system for measuring the registration between at least two integrated circuit layers, one residing over the other, said system comprising:
- an imaging system for generating a top-down of a field of said at least two integrated circuit layers, each of said layers having a respective visible feature in said image;
- means for digitizing said image and processing said digitized image to determine a location of a first feature reference point in said visible feature of one of said layers, and a location of a second feature reference point in said visible feature of the other of said layers, to indicate a relative location of said visible feature of one of said layers, relative to said visible feature of the other of said layers, wherein at least one of said visible features is a non-metrological structure on said one of said integrated circuit layers;
- and
- means for determining if said relative location is within acceptable design limits for said integrated circuit layers.
A method for measuring the registration between integrated circuit layers, said method comprising:
- providing a first integrated circuit layer on a semiconductor substrate, said first integrated circuit layer comprising at least a first visible feature;
- providing a second integrated circuit layer over said first integrated circuit layer, said second integrated circuit layer comprising at least a second visible feature;
- generating a top-down image of a field of said first and second integrated circuit layers, including said first and second visible features;
- digitizing said top-down image to provide a digitized image, and processing said digitized image to determine a relative location of said first visible feature of said first integrated circuit layer, relative to said second visible feature of said second integrated circuit layer by determining a location of a first feature reference point in said first visible feature of said first integrated circuit layer, and a location of a second feature reference point in said second visible feature of said second integrated circuit layer to indicate said relative location, wherein at least one of said visible features is a non-metrological structure on said one of said integrated circuit layers;
- and
- determining if said relative location is within stored acceptable design limits for said first and second integrated circuit layers by comparing said relative location to said stored acceptable design limits.
Dependencies are inferred from the claim text.