Method and apparatus for compensating for timing variances in digital data transmission channels

A high speed digital circuit for use with an N bit digital signal, where N is an integer, comprising:

• a. a source device for receiving said N bit digital data signal;
• b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device;
• c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal;
• and
• d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto;
• said source device outputs a reference signal to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal,
• said source device includes N variable delay units for outputting said N bits, each of said variable delay units associated with and individually controlled by a respective one bit of a phase comparison signal.

A high speed digital circuit for use with an N bit digital data signal, where N is an integer, comprising:

• a. a source device for receiving said N bit digital data signal;
• b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device;
• c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal;
• d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto,
• said high speed digital circuit operating in an initialization condition in which a digital initialization signal having bits of a first predefined unit length initializes said high speed digital circuit, and in an operating condition in which N bits of said N bit digital data signal have a second predefined unit length, wherein said source device includes N AND gates for receiving said N bit digital data signal and said digital initialization signal to produce a gated N bit digital data signal, and variable delay units for receiving said gated N bit digital data signal and outputting an N bit data signal in response thereto, and wherein said first predefined unit length is greater than said second predefined unit length.

A high speed digital circuit for use with an N bit digital data signal, where N is an integer, comprising:

• a. a source device for receiving said N bit digital data signal;
• b. a sink device coupled to said source device and receiving said N bit digital data signal from said source device, said N bit digital data signal having a skew when received by said sink device;
• c. a skew detection circuit in said sink device for detecting said skew in said N bit digital data signal and generating a skew detection signal;
• d. a compensation circuit in said source device for receiving said skew detection signal and compensating for said skew in said N bit digital data signal in response thereto;
• and
• e. a line for supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal, and wherein said sink device includes N correlator units for detecting the delay between each of the N bits of said N bit digital data signal and said reference signal and outputting a phase detection signal.

A method of correcting the skew in an N bit digital data signal, N being an integer, transmitted between a source device and a sink device of an interface, comprising the steps of:

• a. measuring said skew in said N bit digital data signal in said sink device;
• b. generating a skew detection signal in said sink device;
• c. transmitting said skew detection signal from said sink device to said source device;
• d. compensating for said skew in said N bit digital data signal in said source device in response to said skew detection signal;
• e. supplying a reference signal from said source device to said sink device, said reference signal having timing information for phase and delay detection of said skew in said N bit digital data signal;
• and
• f. supplying a synchronization signal between said source device and said sink device;
• and
• said interface operating in an initialization condition and in an operating condition, and further comprising the steps of:
• g. transmitting, in said operating condition, said N bit digital data signal with bits having a first predefined unit length;
• and
• h. transmitting, in said initialization condition, a digital data signal with bits having a second predefined unit length, said second predefined unit length greater than said first predefined unit length.

A high speed digital interface circuit for use with an N bit digital data signal, where N is an integer, comprising:

• a. an N bit bus connecting a source device and a sink device, said N bit digital data signal being received at said sink device with a skew;
• b. said source device comprising;
• i. N variable delay units, each associated with one of N bits, and each of said variable delay units individually controlled for each of said N bits;
• ii. a compensation circuit for compensating for said skew, said compensation circuit including:
• 1. a counter circuit for supplying a reference signal to said sink device;
• 2. an AND gate coupled to said counter circuit;
• and
• 3. N low pass filters, each associated with one of said N bits, and each of said low pass filters coupled to one of said N variable delay units and to said AND gate;
• c. said sink device comprising:
• i. N phase detectors, each associated with one of said N bits, and each of said phase detectors individually controlled for each of said N bits by said reference signal;
• ii. N analog to digital converters, each associated with one of said N bits, coupled to said N phase detectors;
• iii. a skew detection circuit for detecting said skew in said N bit digital data signal and generating a skew detection signal, said skew detection circuit including:
• 1. a counter circuit for receiving said reference signal from said source device;
• and
• 2. an AND gate coupled to said counter circuit;
• d. a line supplying said skew detection signal from said sink device to said source device;
• and
• e. a line supplying said reference signal from said source device to said sink device.