Clock/data recovery circuit
AssigneeNippon Telegraph and Telephone Corporation
InventorsKeiji Kishine, Haruhiko Ichino
Life of this patent
Estimating the term…
Abstract
A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.
Claims18
A clock/data recovery circuit comprising:
- a voltage control oscillator for generating a clock signal of a frequency of 1/K (K=2, 3, . . . ) of a bit rate of an input data signal;
- a delay circuit for delaying said input data signal for timing adjustment;
- a demultiplexer for demultiplexing said input data signal into M demultiplexed signals (M=2, 3, . . . ) by using said clock signal;
- a multiplexer for multiplexing said M demultiplexed signals by using said clock signal;
- a phase comparator for comparing phases of an output signal of said delay circuit and an output signal of said multiplexer;
- a lowpass filter for extracting DC voltage from an output signal of said phase comparator and for inputting said DC voltage to said voltage control oscillator as a control voltage;
- wherein said clock/data recovery circuit outputs said clock signal generated by said voltage control oscillator as a recovery divided clock signal, and outputs said M demultiplexed signals from said demultiplexer as recovery parallel data signals.
A clock/data recovery circuit comprising:
- a voltage control oscillator for generating a clock signal of a frequency of 1/K (K=2, 3, . . . ) of a bit rate of an input data signal;
- a Q divider for receiving said input data signal and for dividing a frequency of said input data signal by Q (Q=2, 3, 4 . . . );
- a first demultiplexer for demultiplexing an output signal of said Q divider into M demultiplexed signals (M=2, 3, . . . ) by using said clock signal;
- a second demultiplexer for demultiplexing said input data signal into N demultiplexed signals by using said clock signal;
- a multiplexer for multiplexing said M demultiplexed signals output from said first demultiplexer into a signal by using said clock signal;
- a phase comparator for comparing phases of an output signal of said Q divider and an output signal of said multiplexer;
- a lowpass filter for extracting DC voltage from an output signal of said phase comparator and for inputting said DC voltage to said voltage control oscillator as a control voltage;
- and
- an m(=N/K) divider for dividing a frequency of an output clock signal of said voltage control oscillator by m;
- wherein said clock/data recovery circuit outputs an output signal of said m(=N/K) divider as a recovery divided signal, and outputs said N demultiplexed signals output from said second demultiplexer as recovery parallel data signals.
A receiving apparatus including a clock/data recovery circuit, said clock/data recovery circuit comprising:
- a voltage control oscillator for generating a clock signal of a frequency of 1/K (K=2, 3, . . . ) of a bit rate of an input data signal;
- a delay circuit for delaying said input data signal for timing adjustment;
- a demultiplexer for demultiplexing said input data signal into M demultiplexed signals (M=2, 3, . . . ) by using said clock signal;
- a multiplexer for multiplexing said M demultiplexed signals by using said clock signal;
- a phase comparator for comparing phases of an output signal of said delay circuit and an output signal of said multiplexer;
- a lowpass filter for extracting DC voltage from an output signal of said phase comparator and inputting said DC voltage to said voltage control oscillator as a control voltage;
- wherein said clock/data recovery circuit outputs said clock signal generated by said voltage control oscillator as a recovery divided clock signal, and outputs said M demultiplexed signals output from said demultiplexer as recovery parallel data signals.
Dependencies are inferred from the claim text.