US 7,095,742 B2Granted

Packet processing unit

AssigneeNEC Corporation

InventorsTeruo Kaganoi, Dai Shizume, Yasuyuki Ikegai

Life of this patent

Estimating the term…

Loading patent…

Abstract

A packet receiving circuit splits the packet received from a transmission channel into a fixed length of cells and outputs the cells, a search key extracting circuit extracts a predetermined search key from the above-mentioned cells, a CAM performs retrieval based on the above-mentioned search key and outputs a memory address corresponding to the search key, a matching entry address receiving and associative data address transmitting circuit calculates the memory address of an associative data memory based on the above-mentioned memory address and outputs the information stored in the associative data memory as associative data, a search result (associative data) receiving circuit receives the above-mentioned associative data and performs header updating and destination address of the above-mentioned cells, and a packet transmitting circuit outputs the above-mentioned cells in the form of a packet to a transmission channel.

Claims20

Dependent claims

A packet processing unit, comprising:

packet receiving means for outputting a packet received via a first transmission channel in the form of split cells of a fixed length,
search key extracting means for extracting a predetermined search key from said cells output from said packet receiving means,
a CAM for performing retrieval of a memory address based on said search key extracted by said search key extracting means and for outputting said memory address,
associative data storing means for storing at least destination information and for outputting information stored at an input memory address,
associative data reading means for calculating a particular memory address of said associative data storing means based on said memory address output from said CAM and for supplying the particular memory address to said associative data storing means,
destination address means for updating a destination address of a particular cell of said cells based on particular information output from said associative data storing means that is stored at said particular memory address in said associative data storing means and for outputting said cells, and
packet transmitting means for combining the cells output from said destination address means into an updated packet and for outputting said updated packet to a second transmission channel,
wherein said packet receiving means, said search key extracting means, said CAM, said associative data reading means, said associative data storing means, said destination address means, and said packet transmitting means are configured to perform processing as stages of a pipeline.

5 more elements

A packet processing unit, comprising:

a packet receiving circuit for receiving a packet over a first transmission channel, and for splitting said packet into a plurality of cells while receiving said packet, and for outputting said plurality of cells, each cell of said plurality of cells having a fixed length;
a search key extracting circuit for extracting one or more search keys from a first cell of said plurality of cells output by said packet receiving circuit and for outputting said one or more search keys;
a content addressable memory for retrieving one or more memory addresses based on said one or more search keys output by said search key extracting circuit, and for outputting said one or more memory addresses;
a matching entry address receiving and associative data address transmitting circuit for calculating one or more particular memory addresses based on said one or more memory addresses output by said content addressable memory, and for outputting said one or more particular memory addresses;
an associative data memory for outputting one or more associative data results that are read from said associative data memory at said one or more particular memory addresses that are output by said matching entry address receiving and associative data address transmitting circuit;
a search result receiving circuit for modifying said first cell of said plurality of cells based on at least one of said one or more associative data results output by said associative data memory, and for outputting said plurality of cells after modifying said first cell;
and
a packet transmitting circuit for combining said plurality of cells output from said search result receiving circuit into a modified packet, and for outputting said modified packet over a second transmission channel.

5 more elements

Dependencies are inferred from the claim text.