Modular register array
AssigneeIntel Corporation
InventorsAndy Spix, Adrian Kaehler, Sunil Sankar, Mike Reitsma
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a register array having a number of entry groups. Each of the entry groups includes multiple entries. Each of the entries has multiple bits. The bits among different entries are grouped into bit groups. The integrated circuit also includes a number of output ports. Each of the output ports has multiple selecting units. Each of the selecting units connects to one of the bit groups. The integrated circuit further includes a number of match ports. Each of the match ports has multiple comparing units. Each of the comparing units connects to one of the bit groups.
Claims27
A circuit comprising:
- a plurality of entries, each of the entries having a number of cells including at least a first cell and a second cell;
- an output port having a number of selecting units including at least a first selecting unit coupled to the first cell of each of the entries and a second selecting unit coupled to the second cell of each of the entries;
- and
- a match port having a number of comparing units including at least a first comparing unit coupled to the first cell of each of the entries and a second comparing unit coupled to the second cell of each of the entries.
An integrated circuit comprising:
- a plurality of entry groups, each of the entry groups including multiple entries, each of the entries including multiple cells, the cells being grouped into a number of bit groups, each of the bit groups including one cell from each of the entries;
- a plurality of output ports, each of the output ports including multiple selecting units;
- each of the selecting units including input nodes coupled to a corresponding bit group, the corresponding bit group being one of the bit groups;
- and
- a plurality of match ports, each of the match ports including multiple comparing units;
- each of the comparing units including input nodes coupled to the corresponding bit group.
A system comprising:
- an integrated circuit including,
- a register array to store data, the register array including at least one entry group having multiple entries, each of the entries including multiple cells, the cells being grouped into a number of bit groups, each of the bit groups including one cell from each of the entries;
- at least one output port to output the data from the register array, the at least one output port having a number of selecting units;
- each of the selecting units coupling to one of the bit groups;
- and
- at least one match port to compare the data stored in the register array with reference data, the at least one match port having a number of comparing units, each of the comparing units coupling to one of the bit groups;
- and
- a dynamic random access memory device coupled to the integrated circuit.
A method comprising:
- accessing a group of entries, each of the entries having a number of bits including at least a first bit and a second bit, the first bit of each of the entries being grouped into a first bit group, the second bit of each of the entries being grouped into a second bit group;
- comparing the first bit of each of the entries with a first reference bit;
- comparing the second bit of each of the entries with a second reference bit;
- and
- activating at least one match signal if the first bit of a selected one of the entries matches the first reference bit and if the second bit of the selected one of the entries matches the second reference bit.
Dependencies are inferred from the claim text.