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US 7,095,673 B2Granted
Semiconductor memory device capable of operating at high speed
AssigneeKabushiki Kaisha Toshiba
InventorYukihiro Fujimoto
Life of this patent
Estimating the term…
Abstract
A plurality of sub-arrays include a plurality of memory elements. First bit line pairs are connected to a plurality of memory elements provided in each of the sub-arrays. Second bit line pairs are provided so as to correspond to a plurality of sub-arrays. The first bit line pairs supply signals to the second bit line pairs. The second bit line pairs are operated at a lower frequency than the first bit line pairs.
Claims18
A semiconductor memory device comprising:
- a plurality of sub-arrays each of which includes a plurality of memory elements;
- first bit line pairs which are provided in each of said plurality of sub-arrays and which are connected to said plurality of memory elements;
- and
- second bit line pairs which are provided so as to correspond to said plurality of sub-arrays and to which the first bit line pairs supply signals and which are operated at a lower frequency than the first bit line pairs.
1 more element
A semiconductor memory device comprising:
- a plurality of sub-arrays each of which includes a plurality of memory elements;
- first bit line pairs which are arranged in a first column in each of said plurality of sub-arrays and which are connected to said plurality of memory elements;
- second bit line pairs which are arranged in a second column in each of said plurality of sub-arrays and which are connected to said plurality of memory elements;
- a first selector which selects either one of the first bit line pair or one of the second bit line pair;
- a second selector which selects either the other of the first bit line pair or the other of the second bit line pair;
- and
- third bit line pairs which are provided so as to correspond to said plurality of sub-arrays and to which the first and second selectors selectively supply signals and which are operated at a lower frequency than the first and second bit line pairs.
4 more elements
A control method of semiconductor memory device comprising:
- reading data of a selected memory cell by one of raising edge and falling edge of a clock signal and supplying the data to first bit line pairs;
- supplying data supplied to the first bit line pairs to second bit line pairs by a frequency of a half of the clock signal;
- and
- selecting one of data of the second bit line pairs by the frequency of the clock signal.
1 more element
Dependencies are inferred from the claim text.