Semiconductor memory having variable memory size and method for refreshing the same

A semiconductor memory device comprising:

• a memory array having a plurality of memory blocks, each of memory blocks having at least one word line;
• and
• a refresh circuit which is operable in a full memory mode and a reduced memory mode, wherein the refresh circuit applies a refresh signal to the all of word lines during each of successive constant refresh cycle times in the full memory mode, and wherein the refresh circuit applies the refresh signal to a subset of the word lines during each of the successive constant refresh cycle times in the reduce memory mode;
• wherein, during each transition from the full memory mode to the reduced memory mode, all of the subset of the word lines receive the refresh signal within the constant refresh cycle time.

A semiconductor memory device which is operable in a full capacity mode and at least one reduced capacity mode, said device comprising:

• a memory array comprising a plurality of memory blocks, each of the memory blocks having at least one word line;
• an address generation circuit which generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods;
• an address sorting circuit which receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block;
• a row decoder which receives the second multi-bit address signal and which selects at least one word line according to the second multi-bit address during a refresh operation.

A memory device operable in a full memory capacity mode and N reduced memory capacity modes, where N is an integer of 1 or more, said memory device comprising:

• a memory array comprising m memory blocks each having at least one word line, where m is an integer 2N or more;
• a refresh reference signal generator which generates a refresh reference signal pulse having a period T;
• an refresh address generation circuit which generates a first n-bit address signal having bits A0, A1, . . . , An, wherein n is an integer greater than or equal to N, and wherein a logic value of the n-bit address signal is sequentially incremented by 1 at each period T of the refresh reference pulse signal;
• a refresh controller which generates a refresh main signal according to a mode control signal and bits A0 . . . A(N−1) of the first address signal;
• an address converter which generates a second n-bit address signal having bits R0, R1, . . . , Rn, wherein the second parallel n-bit address signal is generated at a timing of the refresh main signal, wherein the bits A0 . . . A(N−1) of the first parallel n-bit address signal are respectively output as the bits Rn . . . R(n−(N−1))of the second n-bit address signal, and wherein the bits A(N) . . . An of the first n-bit address signal are respectively output as the bits R0 . . . R(n−(N−2)) of the second n-bit parallel signal;
• and
• a row decoder which addresses a word line of the memory array according to the second n-bit parallel signal at a timing of the refresh main signal.