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US 7,095,669 B2Granted
Refresh for dynamic cells with weak retention
AssigneeInfineon Technologies AG
InventorJong-Hoon Oh
Life of this patent
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Abstract
Methods and circuit configurations for utilizing memory cells having weak retention times are provided. For some embodiments, rows identified as having weak retention cells may be refreshed more often than “normal retention” cells. As an example, if a normal refresh period is TREF, weak retention cells may be refreshed every TREF/2 or TREF/4 (possibly depending on the actual measured retention time).
Claims26
A method for utilizing memory cells in a semiconductor memory device having a weak retention time, comprising:
- refreshing a first set of one or more rows of memory cells at a first frequency by generating a set of regular refresh request signals, wherein at least one of the rows of the first or second sets of rows is refreshed with each regular refresh request signal;
- and
- refreshing a second set of one or more rows of memory cells at a second frequency greater than the first frequency by generating a set of supplemental refresh request signals, wherein at least one of the rows of the second set of rows are refreshed with each supplemental refresh request signal;
- wherein a supplemental refresh request signal, of the set of supplemental refresh request signals, is generated to refresh a given row of the second set of rows in conjunction with a regular refresh signal, of the set of regular refresh request signals, generated to refresh a row having a harmonious address, harmonious addresses being row addresses occurring periodically after the address of the given row and having a defined periodic spacing therebetween.
1 more element
A method of manufacturing a semiconductor memory device, comprising:
- testing rows of memory cells of the device to identify a first set of one or more rows having one or more memory cells with a retention time below a first minimum retention time;
- storing an indication of the first set of rows on the device;
- and
- providing refresh circuitry on the device configured to refresh the first set of rows more frequently than other rows having only memory cells with retention times at or above the first minimum retention time, wherein the refresh circuitry is configured to generate a set of regular refresh request signals and a set of supplemental refresh signals, wherein each of the other rows is refreshed with a regular refresh request signal and each of the first set of rows is refreshed both with a regular refresh request signal and a supplemental refresh signal;
- wherein a supplemental refresh request signal is generated to refresh a given row of the first set of rows in conjunction with a regular refresh signal generated to refresh a row having a harmonious address, harmonious addresses being row addresses occurring periodically after the address of the given row and having a defined periodic spacing therebetween.
2 more elements
A semiconductor memory device, comprising:
- a plurality of rows of memory cells, each having a corresponding row address;
- a plurality of non-volatile memory elements to store row addresses of a first set of one or more of the rows having one or more memory cells with retention times below a first minimum retention time;
- and
- refresh circuitry configured to perform refresh operations for the first set of rows, whose row addresses are stored in the non-volatile memory elements, more frequently than for other rows having only memory cells with retention times at or above the first minimum retention time by generating periodic regular refresh signals to refresh each of the plurality of memory cells within a refresh period and generating fast refresh request signals to additionally refresh each of the first set of rows whose addresses are stored in the non-volatile memory elements;
- wherein a fast refresh request signal is generated to refresh a given row of the first set of rows in conjunction with a regular refresh signal generated to refresh a row having a harmonious address, harmonious addresses being row addresses occurring periodically after the address of the given row and having a defined periodic spacing therebetween.
2 more elements
A semiconductor memory device, comprising:
- N rows of memory cells, wherein N is an integer;
- a plurality of non-volatile memory elements to indicate a first set of one or more of the N rows having one or more memory cells with retention times below a first minimum retention time;
- a refresh address bus;
- a refresh address counter to generate a row address;
- and
- refresh circuitry configured to i) generate regular refresh signals to sequentially refresh the N rows while driving the row address generated by the refresh address counter on the refresh address bus and ii) generate fast refresh signals to additionally refresh the first set of rows while driving row addresses of the first set of rows on the refresh address bus;
- wherein a fast refresh signal is generated to refresh a given row of the first set of rows in conjunction with a regular refresh signal generated to refresh a row having a harmonious address, harmonious addresses being row addresses occurring periodically after the address of the given row and having a defined periodic spacing therebetween.
4 more elements
Dependencies are inferred from the claim text.