Wide databus architecture

A memory comprising:

• plural memory arrays, each array comprising:
• pairs of bit lines, each pair being coupled to a corresponding bit line sense amplifier;
• word lines crossing the bit line pairs;
• and
• storage cells coupled to the bit lines, each having an enable input coupled to a word line;
• pairs of primary databuses parallel to the bit lines, coupled to a plurality of bit line sense amplifiers through first access devices;
• pairs of secondary databuses orthogonal to the primary databuses, centrally located between the plural arrays;
• and
• a plurality of databus sense amplifiers coupled between the primary and secondary databuses.

A method of accessing memory comprising:

• selectively enabling charge storage cells in at least one of plural arrays of charge storage cells, the charge storage cells connected to bit line pairs using word lines crossing the bit line pairs;
• sensing stored charge for enabled charge storage cells by bit line sense amplifiers;
• selectively coupling the bit line sense amplifiers to pairs of primary databuses through first access transistors, the primary databus pairs being parallel to the bit line pairs;
• and
• selectively coupling the primary databus pairs to secondary databus pairs through databus sense amplifiers and second access transistors, the secondary databus pairs being orthogonal to the primary databus pairs and centrally located between the plural arrays.