Method for analyzing defect of SRAM cell
AssigneeHynix Semiconductor Inc.
InventorYun Seok Hong
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Abstract
Disclosed is a method for analyzing a defect of a semiconductor device, and more particularly a method for electrically analyzing a defect of a transistor formed in a cell having a latch structure, such as SRAM or a sense amplifier of DRAM. The defect analyzing method according to the present invention comprises the steps of forming a test SRAM cell array in a scribe lane region of a wafer which is formed with a plurality of SRAM chips, forming a pad portion for testing the SRAM cell array on the scribe lane region, and applying a predetermined test voltage to the SRAM cell array through the pad portion. The respective array cells constituting the SRAM cell array are provide with two word lines, and individual test voltages can be applied through the pad portion to the two word lines, respectively.
Claims11
A method for analyzing a defect of an SRAM cell, the method comprising the steps of:
- forming a test SRAM cell array in a scribe lane region of a wafer which is formed with a plurality of SRAM chips;
- forming a pad portion for testing the SRAM cell array on the scribe lane region;
- and
- applying a predetermined test voltage to the SRAM cell array through the pad portion,
- wherein two switch transistors of the respective array cells constituting the SRAM cell array are connected to two word lines different from each other, and individual test voltages can be applied through the pad portion to the two word lines, respectively.
A method for analyzing a defect of an SRAM cell, the method comprising the steps of:
- forming a test pattern for the test in a scribe lane region, the test pattern being the same as a cell which has a latch structure formed in a cell region;
- and
- applying a test voltage to the test pattern through a pad, thereby performing an electrical test.
Dependencies are inferred from the claim text.