Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM

A semiconductor memory module, on which a plurality of semiconductor memory elements each having a terminal for data signals, a terminal for address/control signals, and a terminal for clock signals, the semiconductor memory module comprising:

• a clock signal line connected to said terminal for clock signals and transmitting said clock signals;
• a data signal line connected to said terminal for data signals and transmitting said data signals;
• a register for setting said address/control signals;
• and
• an address/control line connected in a daisy-chain shape to said terminal for address/control signals from said register and transmitting said address/control signals,
• wherein each of said semiconductor memory elements has a variable delay circuit for delaying said address/control signals or said clock signals for taking in said address/control signals, and
• a delay amount of said variable delay circuit is set so that the sum of said delay amount and a wiring delay time due to a wiring from said register depends on a wiring delay time from said register to the farthest one among said semiconductor memory elements, or a delay amount of said variable delay circuit is set so that the sum of said delay amount and arrival timing of said clock signals to said semiconductor memory elements depends on a wiring delay time from said register to said semiconductor memory elements.