Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device

A method for operating a static random access memory (SRAM) cell, the SRAM cell comprising a latch circuit for data storage, the method comprising:

• adjusting the latch circuit to operate with a first latching strength while the SRAM cell is operating in a data storage mode;
• and
• adjusting the latch circuit to operate with a second latching strength while the SRAM cell is operating in a data write mode,
• wherein the first latching strength is greater than the second latching strength.

A memory circuit comprising:

• a static random access memory (SRAM) cell comprising a latching circuit and a transfer element, the latching circuit comprising a negative differential resistance (NDR) element connected to a data storage node, and the transfer element being coupled between a bit line and the data storage node;
• and
• a biasing circuit for supplying a first voltage potential across the latching circuit while the transfer element is turned off, and for supplying a second voltage potential across the latching circuit while the transfer element is transferring data from the bit line to the storage node,
• wherein a first NDR valley current of the NDR element while the first voltage potential is supplied across the latching circuit is less than a second NDR valley current of the NDR element while the second voltage potential is supplied across the latching circuit.