Flash memory data bus for synchronous burst read page
AssigneeMicron Technology, Inc.
InventorDumitru Cioaca
Life of this patent
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Abstract
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.
Claims31
A method of operating a memory device comprising:
- latching a first set of data words;
- reading data words from the first set of data words while sensing a second set of data words;
- latching a first portion of the second set of data words while reading a last word of the first set of data words;
- and
- latching a second portion of the second set of data words after reading the last word of the first set of data words.
A method of operating a latch circuit comprising:
- latching a first set of data words;
- latching a first portion of a second set of data words while reading a last word of the first set of data words;
- and
- latching a second portion of the second set of data words after reading the last word of the first set of data words.
A method of operating intermediate data word latches, comprising:
- latching a first data word set, wherein the intermediate latch circuit contains a plurality of latch groups, each latch group having a plurality of latch circuits and latches a data word;
- latching a second data word set in the intermediate latch circuit after all but a final data word of the first data word set has been sequentially read, such that all latch groups of the intermediate latch circuit except for a first group of latches that is currently selected and contains the final selected data word are clocked;
- and
- latching only the first group of latches after the final selected data word of the first data word set is sequentially read to complete latching the second data set.
A method of operating intermediate data word latches, comprising:
- latching a first data word set, wherein the intermediate latch circuit contains a plurality of latch groups, each latch group having a plurality of latch circuits and latch a single data word;
- latching a second data word set in the intermediate latch circuit after all but a final data word of the first data word set has been sequentially read from the intermediate latch circuit, such that all latch groups of the intermediate latch circuit except for a first group of latches that is currently selected and contains the final selected data word are clocked;
- and
- latching a final data word of the second data word set in the intermediate latch circuit after the final data word of the first data word set has been read from the intermediate data latch circuit, such that all latch groups of the intermediate latch circuit except for a second group of latches that is currently selected and contains a first selected data word of the second data word set are clocked to complete latching the second data set.
A latch circuit, comprising:
- a plurality of latch groups, each latch group having a plurality of latches and stores a single data word;
- wherein the latch circuit is adapted to latch a first set of data words into the plurality of latch groups of the latch circuit;
- and
- wherein the latch circuit is adapted to latch a second set of data words while a first selected latch group containing a data word of the first set of data words and second selected latch group containing a data word of the second set of data words are sequentially accessed, such that all latch groups of the latch circuit except for the first selected latch group are clocked while the first selected latch group are accessed, and all latch groups of the latch circuit except for the second selected latch group are clocked while the second selected latch group are accessed.
An intermediate latch circuit, comprising:
- a plurality of latch groups, each latch group having a plurality of latch circuits and adapted to store a single data word;
- wherein the intermediate latch circuit is adapted to latch a first set of data words into the plurality of latch groups;
- and
- wherein the intermediate latch circuit is adapted to latch a second set of data words while a first latch group containing a final data word of the first set of data words and a second latch group containing a first data word of the second set of data words are sequentially accessed, such that all latch groups of the intermediate latch circuit except for the first latch group are clocked while the first latch group is accessed, and only the first latch group is clocked while the second latch group is accessed.
Dependencies are inferred from the claim text.